mirror of https://github.com/golang/go.git
559 lines
15 KiB
Go
559 lines
15 KiB
Go
// cmd/9a/lex.c from Vita Nuova.
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//
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// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
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// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
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// Portions Copyright © 1997-1999 Vita Nuova Limited
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// Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
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// Portions Copyright © 2004,2006 Bruce Ellis
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// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
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// Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
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// Portions Copyright © 2009 The Go Authors. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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//go:generate go tool yacc a.y
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package main
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import (
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"cmd/internal/asm"
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"cmd/internal/obj"
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"cmd/internal/obj/ppc64"
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)
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var (
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yyerror = asm.Yyerror
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nullgen obj.Addr
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)
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func main() {
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cinit()
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asm.LSCONST = LSCONST
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asm.LCONST = LCONST
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asm.LFCONST = LFCONST
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asm.LNAME = LNAME
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asm.LVAR = LVAR
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asm.LLAB = LLAB
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asm.Lexinit = lexinit
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asm.Cclean = cclean
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asm.Yyparse = yyparse
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asm.Thechar = '9'
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asm.Thestring = "ppc64"
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asm.Thelinkarch = &ppc64.Linkppc64
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asm.Arches = map[string]*obj.LinkArch{
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"ppc64le": &ppc64.Linkppc64le,
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}
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asm.Main()
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}
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type yy struct{}
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func (yy) Lex(v *yySymType) int {
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var av asm.Yylval
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tok := asm.Yylex(&av)
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v.sym = av.Sym
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v.lval = av.Lval
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v.sval = av.Sval
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v.dval = av.Dval
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return tok
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}
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func (yy) Error(msg string) {
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asm.Yyerror("%s", msg)
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}
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func yyparse() {
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nosched = 0
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yyParse(yy{})
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}
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var lexinit = []asm.Lextab{
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{"SP", LSP, ppc64.D_AUTO},
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{"SB", LSB, ppc64.D_EXTERN},
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{"FP", LFP, ppc64.D_PARAM},
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{"PC", LPC, ppc64.D_BRANCH},
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{"LR", LLR, ppc64.D_LR},
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{"CTR", LCTR, ppc64.D_CTR},
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{"XER", LSPREG, ppc64.D_XER},
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{"MSR", LMSR, ppc64.D_MSR},
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{"FPSCR", LFPSCR, ppc64.D_FPSCR},
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{"SPR", LSPR, ppc64.D_SPR},
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{"DCR", LSPR, ppc64.D_DCR},
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{"CR", LCR, 0},
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{"CR0", LCREG, 0},
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{"CR1", LCREG, 1},
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{"CR2", LCREG, 2},
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{"CR3", LCREG, 3},
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{"CR4", LCREG, 4},
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{"CR5", LCREG, 5},
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{"CR6", LCREG, 6},
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{"CR7", LCREG, 7},
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{"R", LR, 0},
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{"R0", LREG, 0},
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{"R1", LREG, 1},
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{"R2", LREG, 2},
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{"R3", LREG, 3},
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{"R4", LREG, 4},
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{"R5", LREG, 5},
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{"R6", LREG, 6},
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{"R7", LREG, 7},
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{"R8", LREG, 8},
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{"R9", LREG, 9},
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{"R10", LREG, 10},
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{"R11", LREG, 11},
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{"R12", LREG, 12},
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{"R13", LREG, 13},
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{"R14", LREG, 14},
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{"R15", LREG, 15},
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{"R16", LREG, 16},
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{"R17", LREG, 17},
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{"R18", LREG, 18},
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{"R19", LREG, 19},
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{"R20", LREG, 20},
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{"R21", LREG, 21},
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{"R22", LREG, 22},
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{"R23", LREG, 23},
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{"R24", LREG, 24},
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{"R25", LREG, 25},
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{"R26", LREG, 26},
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{"R27", LREG, 27},
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{"R28", LREG, 28},
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{"R29", LREG, 29},
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{"g", LREG, 30}, // avoid unintentionally clobbering g using R30
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{"R31", LREG, 31},
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{"F", LF, 0},
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{"F0", LFREG, 0},
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{"F1", LFREG, 1},
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{"F2", LFREG, 2},
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{"F3", LFREG, 3},
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{"F4", LFREG, 4},
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{"F5", LFREG, 5},
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{"F6", LFREG, 6},
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{"F7", LFREG, 7},
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{"F8", LFREG, 8},
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{"F9", LFREG, 9},
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{"F10", LFREG, 10},
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{"F11", LFREG, 11},
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{"F12", LFREG, 12},
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{"F13", LFREG, 13},
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{"F14", LFREG, 14},
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{"F15", LFREG, 15},
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{"F16", LFREG, 16},
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{"F17", LFREG, 17},
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{"F18", LFREG, 18},
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{"F19", LFREG, 19},
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{"F20", LFREG, 20},
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{"F21", LFREG, 21},
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{"F22", LFREG, 22},
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{"F23", LFREG, 23},
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{"F24", LFREG, 24},
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{"F25", LFREG, 25},
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{"F26", LFREG, 26},
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{"F27", LFREG, 27},
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{"F28", LFREG, 28},
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{"F29", LFREG, 29},
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{"F30", LFREG, 30},
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{"F31", LFREG, 31},
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{"CREQV", LCROP, ppc64.ACREQV},
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{"CRXOR", LCROP, ppc64.ACRXOR},
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{"CRAND", LCROP, ppc64.ACRAND},
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{"CROR", LCROP, ppc64.ACROR},
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{"CRANDN", LCROP, ppc64.ACRANDN},
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{"CRORN", LCROP, ppc64.ACRORN},
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{"CRNAND", LCROP, ppc64.ACRNAND},
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{"CRNOR", LCROP, ppc64.ACRNOR},
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{"ADD", LADDW, ppc64.AADD},
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{"ADDV", LADDW, ppc64.AADDV},
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{"ADDCC", LADDW, ppc64.AADDCC},
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{"ADDVCC", LADDW, ppc64.AADDVCC},
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{"ADDC", LADDW, ppc64.AADDC},
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{"ADDCV", LADDW, ppc64.AADDCV},
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{"ADDCCC", LADDW, ppc64.AADDCCC},
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{"ADDCVCC", LADDW, ppc64.AADDCVCC},
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{"ADDE", LLOGW, ppc64.AADDE},
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{"ADDEV", LLOGW, ppc64.AADDEV},
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{"ADDECC", LLOGW, ppc64.AADDECC},
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{"ADDEVCC", LLOGW, ppc64.AADDEVCC},
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{"ADDME", LABS, ppc64.AADDME},
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{"ADDMEV", LABS, ppc64.AADDMEV},
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{"ADDMECC", LABS, ppc64.AADDMECC},
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{"ADDMEVCC", LABS, ppc64.AADDMEVCC},
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{"ADDZE", LABS, ppc64.AADDZE},
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{"ADDZEV", LABS, ppc64.AADDZEV},
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{"ADDZECC", LABS, ppc64.AADDZECC},
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{"ADDZEVCC", LABS, ppc64.AADDZEVCC},
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{"SUB", LADDW, ppc64.ASUB},
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{"SUBV", LADDW, ppc64.ASUBV},
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{"SUBCC", LADDW, ppc64.ASUBCC},
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{"SUBVCC", LADDW, ppc64.ASUBVCC},
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{"SUBE", LLOGW, ppc64.ASUBE},
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{"SUBECC", LLOGW, ppc64.ASUBECC},
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{"SUBEV", LLOGW, ppc64.ASUBEV},
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{"SUBEVCC", LLOGW, ppc64.ASUBEVCC},
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{"SUBC", LADDW, ppc64.ASUBC},
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{"SUBCCC", LADDW, ppc64.ASUBCCC},
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{"SUBCV", LADDW, ppc64.ASUBCV},
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{"SUBCVCC", LADDW, ppc64.ASUBCVCC},
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{"SUBME", LABS, ppc64.ASUBME},
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{"SUBMEV", LABS, ppc64.ASUBMEV},
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{"SUBMECC", LABS, ppc64.ASUBMECC},
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{"SUBMEVCC", LABS, ppc64.ASUBMEVCC},
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{"SUBZE", LABS, ppc64.ASUBZE},
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{"SUBZEV", LABS, ppc64.ASUBZEV},
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{"SUBZECC", LABS, ppc64.ASUBZECC},
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{"SUBZEVCC", LABS, ppc64.ASUBZEVCC},
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{"AND", LADDW, ppc64.AAND},
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{"ANDCC", LADDW, ppc64.AANDCC}, /* includes andil & andiu */
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{"ANDN", LLOGW, ppc64.AANDN},
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{"ANDNCC", LLOGW, ppc64.AANDNCC},
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{"EQV", LLOGW, ppc64.AEQV},
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{"EQVCC", LLOGW, ppc64.AEQVCC},
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{"NAND", LLOGW, ppc64.ANAND},
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{"NANDCC", LLOGW, ppc64.ANANDCC},
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{"NOR", LLOGW, ppc64.ANOR},
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{"NORCC", LLOGW, ppc64.ANORCC},
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{"OR", LADDW, ppc64.AOR}, /* includes oril & oriu */
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{"ORCC", LADDW, ppc64.AORCC},
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{"ORN", LLOGW, ppc64.AORN},
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{"ORNCC", LLOGW, ppc64.AORNCC},
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{"XOR", LADDW, ppc64.AXOR}, /* includes xoril & xoriu */
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{"XORCC", LLOGW, ppc64.AXORCC},
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{"EXTSB", LABS, ppc64.AEXTSB},
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{"EXTSBCC", LABS, ppc64.AEXTSBCC},
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{"EXTSH", LABS, ppc64.AEXTSH},
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{"EXTSHCC", LABS, ppc64.AEXTSHCC},
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{"CNTLZW", LABS, ppc64.ACNTLZW},
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{"CNTLZWCC", LABS, ppc64.ACNTLZWCC},
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{"RLWMI", LRLWM, ppc64.ARLWMI},
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{"RLWMICC", LRLWM, ppc64.ARLWMICC},
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{"RLWNM", LRLWM, ppc64.ARLWNM},
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{"RLWNMCC", LRLWM, ppc64.ARLWNMCC},
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{"SLW", LSHW, ppc64.ASLW},
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{"SLWCC", LSHW, ppc64.ASLWCC},
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{"SRW", LSHW, ppc64.ASRW},
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{"SRWCC", LSHW, ppc64.ASRWCC},
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{"SRAW", LSHW, ppc64.ASRAW},
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{"SRAWCC", LSHW, ppc64.ASRAWCC},
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{"BR", LBRA, ppc64.ABR},
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{"BC", LBRA, ppc64.ABC},
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{"BCL", LBRA, ppc64.ABC},
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{"BL", LBRA, ppc64.ABL},
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{"BEQ", LBRA, ppc64.ABEQ},
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{"BNE", LBRA, ppc64.ABNE},
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{"BGT", LBRA, ppc64.ABGT},
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{"BGE", LBRA, ppc64.ABGE},
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{"BLT", LBRA, ppc64.ABLT},
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{"BLE", LBRA, ppc64.ABLE},
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{"BVC", LBRA, ppc64.ABVC},
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{"BVS", LBRA, ppc64.ABVS},
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{"CMP", LCMP, ppc64.ACMP},
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{"CMPU", LCMP, ppc64.ACMPU},
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{"CMPW", LCMP, ppc64.ACMPW},
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{"CMPWU", LCMP, ppc64.ACMPWU},
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{"DIVW", LLOGW, ppc64.ADIVW},
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{"DIVWV", LLOGW, ppc64.ADIVWV},
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{"DIVWCC", LLOGW, ppc64.ADIVWCC},
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{"DIVWVCC", LLOGW, ppc64.ADIVWVCC},
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{"DIVWU", LLOGW, ppc64.ADIVWU},
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{"DIVWUV", LLOGW, ppc64.ADIVWUV},
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{"DIVWUCC", LLOGW, ppc64.ADIVWUCC},
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{"DIVWUVCC", LLOGW, ppc64.ADIVWUVCC},
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{"FABS", LFCONV, ppc64.AFABS},
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{"FABSCC", LFCONV, ppc64.AFABSCC},
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{"FNEG", LFCONV, ppc64.AFNEG},
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{"FNEGCC", LFCONV, ppc64.AFNEGCC},
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{"FNABS", LFCONV, ppc64.AFNABS},
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{"FNABSCC", LFCONV, ppc64.AFNABSCC},
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{"FADD", LFADD, ppc64.AFADD},
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{"FADDCC", LFADD, ppc64.AFADDCC},
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{"FSUB", LFADD, ppc64.AFSUB},
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{"FSUBCC", LFADD, ppc64.AFSUBCC},
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{"FMUL", LFADD, ppc64.AFMUL},
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{"FMULCC", LFADD, ppc64.AFMULCC},
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{"FDIV", LFADD, ppc64.AFDIV},
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{"FDIVCC", LFADD, ppc64.AFDIVCC},
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{"FRSP", LFCONV, ppc64.AFRSP},
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{"FRSPCC", LFCONV, ppc64.AFRSPCC},
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{"FCTIW", LFCONV, ppc64.AFCTIW},
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{"FCTIWCC", LFCONV, ppc64.AFCTIWCC},
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{"FCTIWZ", LFCONV, ppc64.AFCTIWZ},
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{"FCTIWZCC", LFCONV, ppc64.AFCTIWZCC},
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{"FMADD", LFMA, ppc64.AFMADD},
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{"FMADDCC", LFMA, ppc64.AFMADDCC},
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{"FMSUB", LFMA, ppc64.AFMSUB},
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{"FMSUBCC", LFMA, ppc64.AFMSUBCC},
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{"FNMADD", LFMA, ppc64.AFNMADD},
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{"FNMADDCC", LFMA, ppc64.AFNMADDCC},
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{"FNMSUB", LFMA, ppc64.AFNMSUB},
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{"FNMSUBCC", LFMA, ppc64.AFNMSUBCC},
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{"FMADDS", LFMA, ppc64.AFMADDS},
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{"FMADDSCC", LFMA, ppc64.AFMADDSCC},
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{"FMSUBS", LFMA, ppc64.AFMSUBS},
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{"FMSUBSCC", LFMA, ppc64.AFMSUBSCC},
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{"FNMADDS", LFMA, ppc64.AFNMADDS},
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{"FNMADDSCC", LFMA, ppc64.AFNMADDSCC},
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{"FNMSUBS", LFMA, ppc64.AFNMSUBS},
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{"FNMSUBSCC", LFMA, ppc64.AFNMSUBSCC},
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{"FCMPU", LFCMP, ppc64.AFCMPU},
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{"FCMPO", LFCMP, ppc64.AFCMPO},
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{"MTFSB0", LMTFSB, ppc64.AMTFSB0},
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{"MTFSB1", LMTFSB, ppc64.AMTFSB1},
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{"FMOVD", LFMOV, ppc64.AFMOVD},
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{"FMOVS", LFMOV, ppc64.AFMOVS},
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{"FMOVDCC", LFCONV, ppc64.AFMOVDCC}, /* fmr. */
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{"GLOBL", LTEXT, ppc64.AGLOBL},
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{"MOVB", LMOVB, ppc64.AMOVB},
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{"MOVBZ", LMOVB, ppc64.AMOVBZ},
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{"MOVBU", LMOVB, ppc64.AMOVBU},
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{"MOVBZU", LMOVB, ppc64.AMOVBZU},
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{"MOVH", LMOVB, ppc64.AMOVH},
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{"MOVHZ", LMOVB, ppc64.AMOVHZ},
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{"MOVHU", LMOVB, ppc64.AMOVHU},
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{"MOVHZU", LMOVB, ppc64.AMOVHZU},
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{"MOVHBR", LXMV, ppc64.AMOVHBR},
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{"MOVWBR", LXMV, ppc64.AMOVWBR},
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{"MOVW", LMOVW, ppc64.AMOVW},
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{"MOVWU", LMOVW, ppc64.AMOVWU},
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{"MOVMW", LMOVMW, ppc64.AMOVMW},
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{"MOVFL", LMOVW, ppc64.AMOVFL},
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{"MULLW", LADDW, ppc64.AMULLW}, /* includes multiply immediate 10-139 */
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{"MULLWV", LLOGW, ppc64.AMULLWV},
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{"MULLWCC", LLOGW, ppc64.AMULLWCC},
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{"MULLWVCC", LLOGW, ppc64.AMULLWVCC},
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{"MULHW", LLOGW, ppc64.AMULHW},
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{"MULHWCC", LLOGW, ppc64.AMULHWCC},
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{"MULHWU", LLOGW, ppc64.AMULHWU},
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{"MULHWUCC", LLOGW, ppc64.AMULHWUCC},
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{"NEG", LABS, ppc64.ANEG},
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{"NEGV", LABS, ppc64.ANEGV},
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{"NEGCC", LABS, ppc64.ANEGCC},
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{"NEGVCC", LABS, ppc64.ANEGVCC},
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{"NOP", LNOP, ppc64.ANOP}, /* ori 0,0,0 */
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{"SYSCALL", LNOP, ppc64.ASYSCALL},
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{"UNDEF", LNOP, ppc64.AUNDEF},
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{"RET", LRETRN, ppc64.ARETURN},
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{"RETURN", LRETRN, ppc64.ARETURN},
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{"RFI", LRETRN, ppc64.ARFI},
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{"RFCI", LRETRN, ppc64.ARFCI},
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{"DATA", LDATA, ppc64.ADATA},
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{"END", LEND, ppc64.AEND},
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{"TEXT", LTEXT, ppc64.ATEXT},
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/* 64-bit instructions */
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{"CNTLZD", LABS, ppc64.ACNTLZD},
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{"CNTLZDCC", LABS, ppc64.ACNTLZDCC},
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{"DIVD", LLOGW, ppc64.ADIVD},
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{"DIVDCC", LLOGW, ppc64.ADIVDCC},
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{"DIVDVCC", LLOGW, ppc64.ADIVDVCC},
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{"DIVDV", LLOGW, ppc64.ADIVDV},
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{"DIVDU", LLOGW, ppc64.ADIVDU},
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{"DIVDUCC", LLOGW, ppc64.ADIVDUCC},
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{"DIVDUVCC", LLOGW, ppc64.ADIVDUVCC},
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{"DIVDUV", LLOGW, ppc64.ADIVDUV},
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{"EXTSW", LABS, ppc64.AEXTSW},
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{"EXTSWCC", LABS, ppc64.AEXTSWCC},
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{"FCTID", LFCONV, ppc64.AFCTID},
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{"FCTIDCC", LFCONV, ppc64.AFCTIDCC},
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{"FCTIDZ", LFCONV, ppc64.AFCTIDZ},
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{"FCTIDZCC", LFCONV, ppc64.AFCTIDZCC},
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{"FCFID", LFCONV, ppc64.AFCFID},
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{"FCFIDCC", LFCONV, ppc64.AFCFIDCC},
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{"LDAR", LXLD, ppc64.ALDAR},
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{"MOVD", LMOVW, ppc64.AMOVD},
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{"MOVDU", LMOVW, ppc64.AMOVDU},
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{"MOVWZ", LMOVW, ppc64.AMOVWZ},
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{"MOVWZU", LMOVW, ppc64.AMOVWZU},
|
|
{"MULHD", LLOGW, ppc64.AMULHD},
|
|
{"MULHDCC", LLOGW, ppc64.AMULHDCC},
|
|
{"MULHDU", LLOGW, ppc64.AMULHDU},
|
|
{"MULHDUCC", LLOGW, ppc64.AMULHDUCC},
|
|
{"MULLD", LADDW, ppc64.AMULLD}, /* includes multiply immediate? */
|
|
{"MULLDCC", LLOGW, ppc64.AMULLDCC},
|
|
{"MULLDVCC", LLOGW, ppc64.AMULLDVCC},
|
|
{"MULLDV", LLOGW, ppc64.AMULLDV},
|
|
{"RFID", LRETRN, ppc64.ARFID},
|
|
{"HRFID", LRETRN, ppc64.AHRFID},
|
|
{"RLDMI", LRLWM, ppc64.ARLDMI},
|
|
{"RLDMICC", LRLWM, ppc64.ARLDMICC},
|
|
{"RLDC", LRLWM, ppc64.ARLDC},
|
|
{"RLDCCC", LRLWM, ppc64.ARLDCCC},
|
|
{"RLDCR", LRLWM, ppc64.ARLDCR},
|
|
{"RLDCRCC", LRLWM, ppc64.ARLDCRCC},
|
|
{"RLDCL", LRLWM, ppc64.ARLDCL},
|
|
{"RLDCLCC", LRLWM, ppc64.ARLDCLCC},
|
|
{"SLBIA", LNOP, ppc64.ASLBIA},
|
|
{"SLBIE", LNOP, ppc64.ASLBIE},
|
|
{"SLBMFEE", LABS, ppc64.ASLBMFEE},
|
|
{"SLBMFEV", LABS, ppc64.ASLBMFEV},
|
|
{"SLBMTE", LABS, ppc64.ASLBMTE},
|
|
{"SLD", LSHW, ppc64.ASLD},
|
|
{"SLDCC", LSHW, ppc64.ASLDCC},
|
|
{"SRD", LSHW, ppc64.ASRD},
|
|
{"SRAD", LSHW, ppc64.ASRAD},
|
|
{"SRADCC", LSHW, ppc64.ASRADCC},
|
|
{"SRDCC", LSHW, ppc64.ASRDCC},
|
|
{"STDCCC", LXST, ppc64.ASTDCCC},
|
|
{"TD", LADDW, ppc64.ATD},
|
|
|
|
/* pseudo instructions */
|
|
{"REM", LLOGW, ppc64.AREM},
|
|
{"REMCC", LLOGW, ppc64.AREMCC},
|
|
{"REMV", LLOGW, ppc64.AREMV},
|
|
{"REMVCC", LLOGW, ppc64.AREMVCC},
|
|
{"REMU", LLOGW, ppc64.AREMU},
|
|
{"REMUCC", LLOGW, ppc64.AREMUCC},
|
|
{"REMUV", LLOGW, ppc64.AREMUV},
|
|
{"REMUVCC", LLOGW, ppc64.AREMUVCC},
|
|
{"REMD", LLOGW, ppc64.AREMD},
|
|
{"REMDCC", LLOGW, ppc64.AREMDCC},
|
|
{"REMDV", LLOGW, ppc64.AREMDV},
|
|
{"REMDVCC", LLOGW, ppc64.AREMDVCC},
|
|
{"REMDU", LLOGW, ppc64.AREMDU},
|
|
{"REMDUCC", LLOGW, ppc64.AREMDUCC},
|
|
{"REMDUV", LLOGW, ppc64.AREMDUV},
|
|
{"REMDUVCC", LLOGW, ppc64.AREMDUVCC},
|
|
|
|
/* special instructions */
|
|
{"DCBF", LXOP, ppc64.ADCBF},
|
|
{"DCBI", LXOP, ppc64.ADCBI},
|
|
{"DCBST", LXOP, ppc64.ADCBST},
|
|
{"DCBT", LXOP, ppc64.ADCBT},
|
|
{"DCBTST", LXOP, ppc64.ADCBTST},
|
|
{"DCBZ", LXOP, ppc64.ADCBZ},
|
|
{"ICBI", LXOP, ppc64.AICBI},
|
|
{"ECIWX", LXLD, ppc64.AECIWX},
|
|
{"ECOWX", LXST, ppc64.AECOWX},
|
|
{"LWAR", LXLD, ppc64.ALWAR},
|
|
{"STWCCC", LXST, ppc64.ASTWCCC},
|
|
{"EIEIO", LRETRN, ppc64.AEIEIO},
|
|
{"TLBIE", LNOP, ppc64.ATLBIE},
|
|
{"TLBIEL", LNOP, ppc64.ATLBIEL},
|
|
{"LSW", LXLD, ppc64.ALSW},
|
|
{"STSW", LXST, ppc64.ASTSW},
|
|
{"ISYNC", LRETRN, ppc64.AISYNC},
|
|
{"SYNC", LRETRN, ppc64.ASYNC},
|
|
{"TLBSYNC", LRETRN, ppc64.ATLBSYNC},
|
|
{"PTESYNC", LRETRN, ppc64.APTESYNC},
|
|
|
|
/* "TW", LADDW, ATW,*/
|
|
{"WORD", LWORD, ppc64.AWORD},
|
|
{"DWORD", LWORD, ppc64.ADWORD},
|
|
{"SCHED", LSCHED, 0},
|
|
{"NOSCHED", LSCHED, 0x80},
|
|
{"PCDATA", LPCDAT, ppc64.APCDATA},
|
|
{"FUNCDATA", LFUNCDAT, ppc64.AFUNCDATA},
|
|
}
|
|
|
|
func cinit() {
|
|
nullgen.Type = ppc64.D_NONE
|
|
nullgen.Name = ppc64.D_NONE
|
|
nullgen.Reg = ppc64.NREG
|
|
nullgen.Scale = ppc64.NREG // replaced Gen.xreg with Prog.scale
|
|
}
|
|
|
|
func cclean() {
|
|
outcode(ppc64.AEND, &nullgen, ppc64.NREG, &nullgen)
|
|
}
|
|
|
|
var lastpc *obj.Prog
|
|
var nosched int
|
|
|
|
func outcode(a int, g1 *obj.Addr, reg int, g2 *obj.Addr) {
|
|
var p *obj.Prog
|
|
var pl *obj.Plist
|
|
|
|
if asm.Pass == 1 {
|
|
goto out
|
|
}
|
|
|
|
if g1.Scale != ppc64.NREG {
|
|
if reg != ppc64.NREG || g2.Scale != ppc64.NREG {
|
|
yyerror("bad addressing modes")
|
|
}
|
|
reg = int(g1.Scale)
|
|
} else if g2.Scale != ppc64.NREG {
|
|
if reg != ppc64.NREG {
|
|
yyerror("bad addressing modes")
|
|
}
|
|
reg = int(g2.Scale)
|
|
}
|
|
|
|
p = asm.Ctxt.Arch.Prg()
|
|
p.As = int16(a)
|
|
p.Lineno = asm.Lineno
|
|
if nosched != 0 {
|
|
p.Mark |= ppc64.NOSCHED
|
|
}
|
|
p.From = *g1
|
|
p.Reg = uint8(reg)
|
|
p.To = *g2
|
|
p.Pc = int64(asm.PC)
|
|
|
|
if lastpc == nil {
|
|
pl = obj.Linknewplist(asm.Ctxt)
|
|
pl.Firstpc = p
|
|
} else {
|
|
lastpc.Link = p
|
|
}
|
|
lastpc = p
|
|
|
|
out:
|
|
if a != ppc64.AGLOBL && a != ppc64.ADATA {
|
|
asm.PC++
|
|
}
|
|
}
|
|
|
|
func outgcode(a int, g1 *obj.Addr, reg int, g2, g3 *obj.Addr) {
|
|
var p *obj.Prog
|
|
var pl *obj.Plist
|
|
|
|
if asm.Pass == 1 {
|
|
goto out
|
|
}
|
|
|
|
p = asm.Ctxt.Arch.Prg()
|
|
p.As = int16(a)
|
|
p.Lineno = asm.Lineno
|
|
if nosched != 0 {
|
|
p.Mark |= ppc64.NOSCHED
|
|
}
|
|
p.From = *g1
|
|
p.Reg = uint8(reg)
|
|
p.From3 = *g2
|
|
p.To = *g3
|
|
p.Pc = int64(asm.PC)
|
|
|
|
if lastpc == nil {
|
|
pl = obj.Linknewplist(asm.Ctxt)
|
|
pl.Firstpc = p
|
|
} else {
|
|
lastpc.Link = p
|
|
}
|
|
lastpc = p
|
|
|
|
out:
|
|
if a != ppc64.AGLOBL && a != ppc64.ADATA {
|
|
asm.PC++
|
|
}
|
|
}
|