mirror of https://github.com/golang/go.git
777 lines
20 KiB
Go
777 lines
20 KiB
Go
// Copyright 2016 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package arm64
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import (
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"math"
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"cmd/compile/internal/gc"
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"cmd/compile/internal/ssa"
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"cmd/internal/obj"
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"cmd/internal/obj/arm64"
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)
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// loadByType returns the load instruction of the given type.
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func loadByType(t ssa.Type) obj.As {
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if t.IsFloat() {
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switch t.Size() {
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case 4:
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return arm64.AFMOVS
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case 8:
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return arm64.AFMOVD
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}
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} else {
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switch t.Size() {
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case 1:
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if t.IsSigned() {
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return arm64.AMOVB
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} else {
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return arm64.AMOVBU
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}
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case 2:
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if t.IsSigned() {
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return arm64.AMOVH
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} else {
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return arm64.AMOVHU
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}
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case 4:
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if t.IsSigned() {
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return arm64.AMOVW
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} else {
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return arm64.AMOVWU
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}
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case 8:
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return arm64.AMOVD
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}
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}
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panic("bad load type")
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}
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// storeByType returns the store instruction of the given type.
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func storeByType(t ssa.Type) obj.As {
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if t.IsFloat() {
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switch t.Size() {
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case 4:
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return arm64.AFMOVS
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case 8:
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return arm64.AFMOVD
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}
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} else {
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switch t.Size() {
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case 1:
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return arm64.AMOVB
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case 2:
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return arm64.AMOVH
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case 4:
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return arm64.AMOVW
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case 8:
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return arm64.AMOVD
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}
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}
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panic("bad store type")
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}
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// makeshift encodes a register shifted by a constant, used as an Offset in Prog
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func makeshift(reg int16, typ int64, s int64) int64 {
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return int64(reg&31)<<16 | typ | (s&63)<<10
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}
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// genshift generates a Prog for r = r0 op (r1 shifted by s)
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func genshift(as obj.As, r0, r1, r int16, typ int64, s int64) *obj.Prog {
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p := gc.Prog(as)
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p.From.Type = obj.TYPE_SHIFT
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p.From.Offset = makeshift(r1, typ, s)
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p.Reg = r0
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if r != 0 {
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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}
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return p
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}
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func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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switch v.Op {
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case ssa.OpCopy, ssa.OpARM64MOVDconvert, ssa.OpARM64MOVDreg:
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if v.Type.IsMemory() {
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return
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}
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x := v.Args[0].Reg()
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y := v.Reg()
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if x == y {
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return
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}
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as := arm64.AMOVD
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if v.Type.IsFloat() {
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switch v.Type.Size() {
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case 4:
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as = arm64.AFMOVS
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case 8:
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as = arm64.AFMOVD
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default:
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panic("bad float size")
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}
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}
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p := gc.Prog(as)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = x
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p.To.Type = obj.TYPE_REG
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p.To.Reg = y
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case ssa.OpARM64MOVDnop:
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if v.Reg() != v.Args[0].Reg() {
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v.Fatalf("input[0] and output not in same register %s", v.LongString())
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}
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// nothing to do
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case ssa.OpLoadReg:
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if v.Type.IsFlags() {
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v.Fatalf("load flags not implemented: %v", v.LongString())
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return
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}
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p := gc.Prog(loadByType(v.Type))
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gc.AddrAuto(&p.From, v.Args[0])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpStoreReg:
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if v.Type.IsFlags() {
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v.Fatalf("store flags not implemented: %v", v.LongString())
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return
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}
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p := gc.Prog(storeByType(v.Type))
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[0].Reg()
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gc.AddrAuto(&p.To, v)
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case ssa.OpARM64ADD,
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ssa.OpARM64SUB,
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ssa.OpARM64AND,
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ssa.OpARM64OR,
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ssa.OpARM64XOR,
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ssa.OpARM64BIC,
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ssa.OpARM64MUL,
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ssa.OpARM64MULW,
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ssa.OpARM64MULH,
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ssa.OpARM64UMULH,
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ssa.OpARM64MULL,
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ssa.OpARM64UMULL,
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ssa.OpARM64DIV,
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ssa.OpARM64UDIV,
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ssa.OpARM64DIVW,
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ssa.OpARM64UDIVW,
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ssa.OpARM64MOD,
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ssa.OpARM64UMOD,
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ssa.OpARM64MODW,
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ssa.OpARM64UMODW,
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ssa.OpARM64SLL,
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ssa.OpARM64SRL,
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ssa.OpARM64SRA,
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ssa.OpARM64FADDS,
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ssa.OpARM64FADDD,
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ssa.OpARM64FSUBS,
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ssa.OpARM64FSUBD,
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ssa.OpARM64FMULS,
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ssa.OpARM64FMULD,
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ssa.OpARM64FDIVS,
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ssa.OpARM64FDIVD:
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r := v.Reg()
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r1 := v.Args[0].Reg()
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r2 := v.Args[1].Reg()
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = r2
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p.Reg = r1
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.OpARM64ADDconst,
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ssa.OpARM64SUBconst,
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ssa.OpARM64ANDconst,
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ssa.OpARM64ORconst,
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ssa.OpARM64XORconst,
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ssa.OpARM64BICconst,
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ssa.OpARM64SLLconst,
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ssa.OpARM64SRLconst,
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ssa.OpARM64SRAconst,
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ssa.OpARM64RORconst,
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ssa.OpARM64RORWconst:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.Reg = v.Args[0].Reg()
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpARM64ADDshiftLL,
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ssa.OpARM64SUBshiftLL,
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ssa.OpARM64ANDshiftLL,
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ssa.OpARM64ORshiftLL,
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ssa.OpARM64XORshiftLL,
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ssa.OpARM64BICshiftLL:
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genshift(v.Op.Asm(), v.Args[0].Reg(), v.Args[1].Reg(), v.Reg(), arm64.SHIFT_LL, v.AuxInt)
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case ssa.OpARM64ADDshiftRL,
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ssa.OpARM64SUBshiftRL,
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ssa.OpARM64ANDshiftRL,
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ssa.OpARM64ORshiftRL,
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ssa.OpARM64XORshiftRL,
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ssa.OpARM64BICshiftRL:
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genshift(v.Op.Asm(), v.Args[0].Reg(), v.Args[1].Reg(), v.Reg(), arm64.SHIFT_LR, v.AuxInt)
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case ssa.OpARM64ADDshiftRA,
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ssa.OpARM64SUBshiftRA,
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ssa.OpARM64ANDshiftRA,
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ssa.OpARM64ORshiftRA,
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ssa.OpARM64XORshiftRA,
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ssa.OpARM64BICshiftRA:
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genshift(v.Op.Asm(), v.Args[0].Reg(), v.Args[1].Reg(), v.Reg(), arm64.SHIFT_AR, v.AuxInt)
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case ssa.OpARM64MOVDconst:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpARM64FMOVSconst,
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ssa.OpARM64FMOVDconst:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_FCONST
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p.From.Val = math.Float64frombits(uint64(v.AuxInt))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpARM64CMP,
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ssa.OpARM64CMPW,
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ssa.OpARM64CMN,
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ssa.OpARM64CMNW,
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ssa.OpARM64FCMPS,
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ssa.OpARM64FCMPD:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[1].Reg()
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p.Reg = v.Args[0].Reg()
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case ssa.OpARM64CMPconst,
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ssa.OpARM64CMPWconst,
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ssa.OpARM64CMNconst,
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ssa.OpARM64CMNWconst:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.Reg = v.Args[0].Reg()
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case ssa.OpARM64CMPshiftLL:
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genshift(v.Op.Asm(), v.Args[0].Reg(), v.Args[1].Reg(), 0, arm64.SHIFT_LL, v.AuxInt)
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case ssa.OpARM64CMPshiftRL:
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genshift(v.Op.Asm(), v.Args[0].Reg(), v.Args[1].Reg(), 0, arm64.SHIFT_LR, v.AuxInt)
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case ssa.OpARM64CMPshiftRA:
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genshift(v.Op.Asm(), v.Args[0].Reg(), v.Args[1].Reg(), 0, arm64.SHIFT_AR, v.AuxInt)
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case ssa.OpARM64MOVDaddr:
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p := gc.Prog(arm64.AMOVD)
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p.From.Type = obj.TYPE_ADDR
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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var wantreg string
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// MOVD $sym+off(base), R
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// the assembler expands it as the following:
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// - base is SP: add constant offset to SP (R13)
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// when constant is large, tmp register (R11) may be used
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// - base is SB: load external address from constant pool (use relocation)
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switch v.Aux.(type) {
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default:
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v.Fatalf("aux is of unknown type %T", v.Aux)
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case *ssa.ExternSymbol:
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wantreg = "SB"
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gc.AddAux(&p.From, v)
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case *ssa.ArgSymbol, *ssa.AutoSymbol:
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wantreg = "SP"
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gc.AddAux(&p.From, v)
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case nil:
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// No sym, just MOVD $off(SP), R
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wantreg = "SP"
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p.From.Reg = arm64.REGSP
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p.From.Offset = v.AuxInt
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}
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if reg := v.Args[0].RegName(); reg != wantreg {
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v.Fatalf("bad reg %s for symbol type %T, want %s", reg, v.Aux, wantreg)
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}
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case ssa.OpARM64MOVBload,
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ssa.OpARM64MOVBUload,
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ssa.OpARM64MOVHload,
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ssa.OpARM64MOVHUload,
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ssa.OpARM64MOVWload,
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ssa.OpARM64MOVWUload,
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ssa.OpARM64MOVDload,
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ssa.OpARM64FMOVSload,
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ssa.OpARM64FMOVDload:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = v.Args[0].Reg()
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gc.AddAux(&p.From, v)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpARM64LDAR,
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ssa.OpARM64LDARW:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = v.Args[0].Reg()
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gc.AddAux(&p.From, v)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg0()
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case ssa.OpARM64MOVBstore,
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ssa.OpARM64MOVHstore,
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ssa.OpARM64MOVWstore,
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ssa.OpARM64MOVDstore,
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ssa.OpARM64FMOVSstore,
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ssa.OpARM64FMOVDstore,
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ssa.OpARM64STLR,
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ssa.OpARM64STLRW:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[1].Reg()
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p.To.Type = obj.TYPE_MEM
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p.To.Reg = v.Args[0].Reg()
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gc.AddAux(&p.To, v)
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case ssa.OpARM64MOVBstorezero,
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ssa.OpARM64MOVHstorezero,
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ssa.OpARM64MOVWstorezero,
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ssa.OpARM64MOVDstorezero:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = arm64.REGZERO
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p.To.Type = obj.TYPE_MEM
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p.To.Reg = v.Args[0].Reg()
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gc.AddAux(&p.To, v)
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case ssa.OpARM64LoweredAtomicExchange64,
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ssa.OpARM64LoweredAtomicExchange32:
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// LDAXR (Rarg0), Rout
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// STLXR Rarg1, (Rarg0), Rtmp
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// CBNZ Rtmp, -2(PC)
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ld := arm64.ALDAXR
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st := arm64.ASTLXR
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if v.Op == ssa.OpARM64LoweredAtomicExchange32 {
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ld = arm64.ALDAXRW
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st = arm64.ASTLXRW
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}
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r0 := v.Args[0].Reg()
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r1 := v.Args[1].Reg()
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out := v.Reg0()
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p := gc.Prog(ld)
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = r0
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p.To.Type = obj.TYPE_REG
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p.To.Reg = out
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p1 := gc.Prog(st)
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p1.From.Type = obj.TYPE_REG
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p1.From.Reg = r1
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p1.To.Type = obj.TYPE_MEM
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p1.To.Reg = r0
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p1.RegTo2 = arm64.REGTMP
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p2 := gc.Prog(arm64.ACBNZ)
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p2.From.Type = obj.TYPE_REG
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p2.From.Reg = arm64.REGTMP
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p2.To.Type = obj.TYPE_BRANCH
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gc.Patch(p2, p)
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case ssa.OpARM64LoweredAtomicAdd64,
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ssa.OpARM64LoweredAtomicAdd32:
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// LDAXR (Rarg0), Rout
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// ADD Rarg1, Rout
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// STLXR Rout, (Rarg0), Rtmp
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// CBNZ Rtmp, -3(PC)
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ld := arm64.ALDAXR
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st := arm64.ASTLXR
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if v.Op == ssa.OpARM64LoweredAtomicAdd32 {
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ld = arm64.ALDAXRW
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st = arm64.ASTLXRW
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}
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r0 := v.Args[0].Reg()
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r1 := v.Args[1].Reg()
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out := v.Reg0()
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p := gc.Prog(ld)
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = r0
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p.To.Type = obj.TYPE_REG
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p.To.Reg = out
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p1 := gc.Prog(arm64.AADD)
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p1.From.Type = obj.TYPE_REG
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p1.From.Reg = r1
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p1.To.Type = obj.TYPE_REG
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p1.To.Reg = out
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p2 := gc.Prog(st)
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p2.From.Type = obj.TYPE_REG
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p2.From.Reg = out
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p2.To.Type = obj.TYPE_MEM
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p2.To.Reg = r0
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p2.RegTo2 = arm64.REGTMP
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p3 := gc.Prog(arm64.ACBNZ)
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p3.From.Type = obj.TYPE_REG
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p3.From.Reg = arm64.REGTMP
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p3.To.Type = obj.TYPE_BRANCH
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gc.Patch(p3, p)
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case ssa.OpARM64LoweredAtomicCas64,
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ssa.OpARM64LoweredAtomicCas32:
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// LDAXR (Rarg0), Rtmp
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// CMP Rarg1, Rtmp
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// BNE 3(PC)
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// STLXR Rarg2, (Rarg0), Rtmp
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// CBNZ Rtmp, -4(PC)
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// CSET EQ, Rout
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ld := arm64.ALDAXR
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st := arm64.ASTLXR
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cmp := arm64.ACMP
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if v.Op == ssa.OpARM64LoweredAtomicCas32 {
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ld = arm64.ALDAXRW
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st = arm64.ASTLXRW
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cmp = arm64.ACMPW
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}
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r0 := v.Args[0].Reg()
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r1 := v.Args[1].Reg()
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r2 := v.Args[2].Reg()
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out := v.Reg0()
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p := gc.Prog(ld)
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = r0
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p.To.Type = obj.TYPE_REG
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p.To.Reg = arm64.REGTMP
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p1 := gc.Prog(cmp)
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p1.From.Type = obj.TYPE_REG
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p1.From.Reg = r1
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p1.Reg = arm64.REGTMP
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p2 := gc.Prog(arm64.ABNE)
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p2.To.Type = obj.TYPE_BRANCH
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p3 := gc.Prog(st)
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p3.From.Type = obj.TYPE_REG
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p3.From.Reg = r2
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p3.To.Type = obj.TYPE_MEM
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p3.To.Reg = r0
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p3.RegTo2 = arm64.REGTMP
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p4 := gc.Prog(arm64.ACBNZ)
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p4.From.Type = obj.TYPE_REG
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p4.From.Reg = arm64.REGTMP
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p4.To.Type = obj.TYPE_BRANCH
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gc.Patch(p4, p)
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p5 := gc.Prog(arm64.ACSET)
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p5.From.Type = obj.TYPE_REG // assembler encodes conditional bits in Reg
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p5.From.Reg = arm64.COND_EQ
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p5.To.Type = obj.TYPE_REG
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p5.To.Reg = out
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gc.Patch(p2, p5)
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case ssa.OpARM64LoweredAtomicAnd8,
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ssa.OpARM64LoweredAtomicOr8:
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// LDAXRB (Rarg0), Rtmp
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// AND/OR Rarg1, Rtmp
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// STLXRB Rtmp, (Rarg0), Rtmp
|
|
// CBNZ Rtmp, -3(PC)
|
|
r0 := v.Args[0].Reg()
|
|
r1 := v.Args[1].Reg()
|
|
p := gc.Prog(arm64.ALDAXRB)
|
|
p.From.Type = obj.TYPE_MEM
|
|
p.From.Reg = r0
|
|
p.To.Type = obj.TYPE_REG
|
|
p.To.Reg = arm64.REGTMP
|
|
p1 := gc.Prog(v.Op.Asm())
|
|
p1.From.Type = obj.TYPE_REG
|
|
p1.From.Reg = r1
|
|
p1.To.Type = obj.TYPE_REG
|
|
p1.To.Reg = arm64.REGTMP
|
|
p2 := gc.Prog(arm64.ASTLXRB)
|
|
p2.From.Type = obj.TYPE_REG
|
|
p2.From.Reg = arm64.REGTMP
|
|
p2.To.Type = obj.TYPE_MEM
|
|
p2.To.Reg = r0
|
|
p2.RegTo2 = arm64.REGTMP
|
|
p3 := gc.Prog(arm64.ACBNZ)
|
|
p3.From.Type = obj.TYPE_REG
|
|
p3.From.Reg = arm64.REGTMP
|
|
p3.To.Type = obj.TYPE_BRANCH
|
|
gc.Patch(p3, p)
|
|
case ssa.OpARM64MOVBreg,
|
|
ssa.OpARM64MOVBUreg,
|
|
ssa.OpARM64MOVHreg,
|
|
ssa.OpARM64MOVHUreg,
|
|
ssa.OpARM64MOVWreg,
|
|
ssa.OpARM64MOVWUreg:
|
|
a := v.Args[0]
|
|
for a.Op == ssa.OpCopy || a.Op == ssa.OpARM64MOVDreg {
|
|
a = a.Args[0]
|
|
}
|
|
if a.Op == ssa.OpLoadReg {
|
|
t := a.Type
|
|
switch {
|
|
case v.Op == ssa.OpARM64MOVBreg && t.Size() == 1 && t.IsSigned(),
|
|
v.Op == ssa.OpARM64MOVBUreg && t.Size() == 1 && !t.IsSigned(),
|
|
v.Op == ssa.OpARM64MOVHreg && t.Size() == 2 && t.IsSigned(),
|
|
v.Op == ssa.OpARM64MOVHUreg && t.Size() == 2 && !t.IsSigned(),
|
|
v.Op == ssa.OpARM64MOVWreg && t.Size() == 4 && t.IsSigned(),
|
|
v.Op == ssa.OpARM64MOVWUreg && t.Size() == 4 && !t.IsSigned():
|
|
// arg is a proper-typed load, already zero/sign-extended, don't extend again
|
|
if v.Reg() == v.Args[0].Reg() {
|
|
return
|
|
}
|
|
p := gc.Prog(arm64.AMOVD)
|
|
p.From.Type = obj.TYPE_REG
|
|
p.From.Reg = v.Args[0].Reg()
|
|
p.To.Type = obj.TYPE_REG
|
|
p.To.Reg = v.Reg()
|
|
return
|
|
default:
|
|
}
|
|
}
|
|
fallthrough
|
|
case ssa.OpARM64MVN,
|
|
ssa.OpARM64NEG,
|
|
ssa.OpARM64FNEGS,
|
|
ssa.OpARM64FNEGD,
|
|
ssa.OpARM64FSQRTD,
|
|
ssa.OpARM64FCVTZSSW,
|
|
ssa.OpARM64FCVTZSDW,
|
|
ssa.OpARM64FCVTZUSW,
|
|
ssa.OpARM64FCVTZUDW,
|
|
ssa.OpARM64FCVTZSS,
|
|
ssa.OpARM64FCVTZSD,
|
|
ssa.OpARM64FCVTZUS,
|
|
ssa.OpARM64FCVTZUD,
|
|
ssa.OpARM64SCVTFWS,
|
|
ssa.OpARM64SCVTFWD,
|
|
ssa.OpARM64SCVTFS,
|
|
ssa.OpARM64SCVTFD,
|
|
ssa.OpARM64UCVTFWS,
|
|
ssa.OpARM64UCVTFWD,
|
|
ssa.OpARM64UCVTFS,
|
|
ssa.OpARM64UCVTFD,
|
|
ssa.OpARM64FCVTSD,
|
|
ssa.OpARM64FCVTDS,
|
|
ssa.OpARM64REV,
|
|
ssa.OpARM64REVW,
|
|
ssa.OpARM64REV16W,
|
|
ssa.OpARM64RBIT,
|
|
ssa.OpARM64RBITW,
|
|
ssa.OpARM64CLZ,
|
|
ssa.OpARM64CLZW:
|
|
p := gc.Prog(v.Op.Asm())
|
|
p.From.Type = obj.TYPE_REG
|
|
p.From.Reg = v.Args[0].Reg()
|
|
p.To.Type = obj.TYPE_REG
|
|
p.To.Reg = v.Reg()
|
|
case ssa.OpARM64CSELULT,
|
|
ssa.OpARM64CSELULT0:
|
|
r1 := int16(arm64.REGZERO)
|
|
if v.Op == ssa.OpARM64CSELULT {
|
|
r1 = v.Args[1].Reg()
|
|
}
|
|
p := gc.Prog(v.Op.Asm())
|
|
p.From.Type = obj.TYPE_REG // assembler encodes conditional bits in Reg
|
|
p.From.Reg = arm64.COND_LO
|
|
p.Reg = v.Args[0].Reg()
|
|
p.From3 = &obj.Addr{Type: obj.TYPE_REG, Reg: r1}
|
|
p.To.Type = obj.TYPE_REG
|
|
p.To.Reg = v.Reg()
|
|
case ssa.OpARM64DUFFZERO:
|
|
// runtime.duffzero expects start address - 8 in R16
|
|
p := gc.Prog(arm64.ASUB)
|
|
p.From.Type = obj.TYPE_CONST
|
|
p.From.Offset = 8
|
|
p.Reg = v.Args[0].Reg()
|
|
p.To.Type = obj.TYPE_REG
|
|
p.To.Reg = arm64.REG_R16
|
|
p = gc.Prog(obj.ADUFFZERO)
|
|
p.To.Type = obj.TYPE_MEM
|
|
p.To.Name = obj.NAME_EXTERN
|
|
p.To.Sym = gc.Duffzero
|
|
p.To.Offset = v.AuxInt
|
|
case ssa.OpARM64LoweredZero:
|
|
// MOVD.P ZR, 8(R16)
|
|
// CMP Rarg1, R16
|
|
// BLE -2(PC)
|
|
// arg1 is the address of the last element to zero
|
|
p := gc.Prog(arm64.AMOVD)
|
|
p.Scond = arm64.C_XPOST
|
|
p.From.Type = obj.TYPE_REG
|
|
p.From.Reg = arm64.REGZERO
|
|
p.To.Type = obj.TYPE_MEM
|
|
p.To.Reg = arm64.REG_R16
|
|
p.To.Offset = 8
|
|
p2 := gc.Prog(arm64.ACMP)
|
|
p2.From.Type = obj.TYPE_REG
|
|
p2.From.Reg = v.Args[1].Reg()
|
|
p2.Reg = arm64.REG_R16
|
|
p3 := gc.Prog(arm64.ABLE)
|
|
p3.To.Type = obj.TYPE_BRANCH
|
|
gc.Patch(p3, p)
|
|
case ssa.OpARM64DUFFCOPY:
|
|
p := gc.Prog(obj.ADUFFCOPY)
|
|
p.To.Type = obj.TYPE_MEM
|
|
p.To.Name = obj.NAME_EXTERN
|
|
p.To.Sym = gc.Duffcopy
|
|
p.To.Offset = v.AuxInt
|
|
case ssa.OpARM64LoweredMove:
|
|
// MOVD.P 8(R16), Rtmp
|
|
// MOVD.P Rtmp, 8(R17)
|
|
// CMP Rarg2, R16
|
|
// BLE -3(PC)
|
|
// arg2 is the address of the last element of src
|
|
p := gc.Prog(arm64.AMOVD)
|
|
p.Scond = arm64.C_XPOST
|
|
p.From.Type = obj.TYPE_MEM
|
|
p.From.Reg = arm64.REG_R16
|
|
p.From.Offset = 8
|
|
p.To.Type = obj.TYPE_REG
|
|
p.To.Reg = arm64.REGTMP
|
|
p2 := gc.Prog(arm64.AMOVD)
|
|
p2.Scond = arm64.C_XPOST
|
|
p2.From.Type = obj.TYPE_REG
|
|
p2.From.Reg = arm64.REGTMP
|
|
p2.To.Type = obj.TYPE_MEM
|
|
p2.To.Reg = arm64.REG_R17
|
|
p2.To.Offset = 8
|
|
p3 := gc.Prog(arm64.ACMP)
|
|
p3.From.Type = obj.TYPE_REG
|
|
p3.From.Reg = v.Args[2].Reg()
|
|
p3.Reg = arm64.REG_R16
|
|
p4 := gc.Prog(arm64.ABLE)
|
|
p4.To.Type = obj.TYPE_BRANCH
|
|
gc.Patch(p4, p)
|
|
case ssa.OpARM64CALLstatic, ssa.OpARM64CALLclosure, ssa.OpARM64CALLinter:
|
|
s.Call(v)
|
|
case ssa.OpARM64LoweredNilCheck:
|
|
// Issue a load which will fault if arg is nil.
|
|
p := gc.Prog(arm64.AMOVB)
|
|
p.From.Type = obj.TYPE_MEM
|
|
p.From.Reg = v.Args[0].Reg()
|
|
gc.AddAux(&p.From, v)
|
|
p.To.Type = obj.TYPE_REG
|
|
p.To.Reg = arm64.REGTMP
|
|
if gc.Debug_checknil != 0 && v.Pos.Line() > 1 { // v.Line==1 in generated wrappers
|
|
gc.Warnl(v.Pos, "generated nil check")
|
|
}
|
|
case ssa.OpARM64Equal,
|
|
ssa.OpARM64NotEqual,
|
|
ssa.OpARM64LessThan,
|
|
ssa.OpARM64LessEqual,
|
|
ssa.OpARM64GreaterThan,
|
|
ssa.OpARM64GreaterEqual,
|
|
ssa.OpARM64LessThanU,
|
|
ssa.OpARM64LessEqualU,
|
|
ssa.OpARM64GreaterThanU,
|
|
ssa.OpARM64GreaterEqualU:
|
|
// generate boolean values using CSET
|
|
p := gc.Prog(arm64.ACSET)
|
|
p.From.Type = obj.TYPE_REG // assembler encodes conditional bits in Reg
|
|
p.From.Reg = condBits[v.Op]
|
|
p.To.Type = obj.TYPE_REG
|
|
p.To.Reg = v.Reg()
|
|
case ssa.OpARM64LoweredGetClosurePtr:
|
|
// Closure pointer is R26 (arm64.REGCTXT).
|
|
gc.CheckLoweredGetClosurePtr(v)
|
|
case ssa.OpARM64FlagEQ,
|
|
ssa.OpARM64FlagLT_ULT,
|
|
ssa.OpARM64FlagLT_UGT,
|
|
ssa.OpARM64FlagGT_ULT,
|
|
ssa.OpARM64FlagGT_UGT:
|
|
v.Fatalf("Flag* ops should never make it to codegen %v", v.LongString())
|
|
case ssa.OpARM64InvertFlags:
|
|
v.Fatalf("InvertFlags should never make it to codegen %v", v.LongString())
|
|
default:
|
|
v.Fatalf("genValue not implemented: %s", v.LongString())
|
|
}
|
|
}
|
|
|
|
var condBits = map[ssa.Op]int16{
|
|
ssa.OpARM64Equal: arm64.COND_EQ,
|
|
ssa.OpARM64NotEqual: arm64.COND_NE,
|
|
ssa.OpARM64LessThan: arm64.COND_LT,
|
|
ssa.OpARM64LessThanU: arm64.COND_LO,
|
|
ssa.OpARM64LessEqual: arm64.COND_LE,
|
|
ssa.OpARM64LessEqualU: arm64.COND_LS,
|
|
ssa.OpARM64GreaterThan: arm64.COND_GT,
|
|
ssa.OpARM64GreaterThanU: arm64.COND_HI,
|
|
ssa.OpARM64GreaterEqual: arm64.COND_GE,
|
|
ssa.OpARM64GreaterEqualU: arm64.COND_HS,
|
|
}
|
|
|
|
var blockJump = map[ssa.BlockKind]struct {
|
|
asm, invasm obj.As
|
|
}{
|
|
ssa.BlockARM64EQ: {arm64.ABEQ, arm64.ABNE},
|
|
ssa.BlockARM64NE: {arm64.ABNE, arm64.ABEQ},
|
|
ssa.BlockARM64LT: {arm64.ABLT, arm64.ABGE},
|
|
ssa.BlockARM64GE: {arm64.ABGE, arm64.ABLT},
|
|
ssa.BlockARM64LE: {arm64.ABLE, arm64.ABGT},
|
|
ssa.BlockARM64GT: {arm64.ABGT, arm64.ABLE},
|
|
ssa.BlockARM64ULT: {arm64.ABLO, arm64.ABHS},
|
|
ssa.BlockARM64UGE: {arm64.ABHS, arm64.ABLO},
|
|
ssa.BlockARM64UGT: {arm64.ABHI, arm64.ABLS},
|
|
ssa.BlockARM64ULE: {arm64.ABLS, arm64.ABHI},
|
|
ssa.BlockARM64Z: {arm64.ACBZ, arm64.ACBNZ},
|
|
ssa.BlockARM64NZ: {arm64.ACBNZ, arm64.ACBZ},
|
|
ssa.BlockARM64ZW: {arm64.ACBZW, arm64.ACBNZW},
|
|
ssa.BlockARM64NZW: {arm64.ACBNZW, arm64.ACBZW},
|
|
}
|
|
|
|
func ssaGenBlock(s *gc.SSAGenState, b, next *ssa.Block) {
|
|
s.SetPos(b.Pos)
|
|
|
|
switch b.Kind {
|
|
case ssa.BlockPlain:
|
|
if b.Succs[0].Block() != next {
|
|
p := gc.Prog(obj.AJMP)
|
|
p.To.Type = obj.TYPE_BRANCH
|
|
s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[0].Block()})
|
|
}
|
|
|
|
case ssa.BlockDefer:
|
|
// defer returns in R0:
|
|
// 0 if we should continue executing
|
|
// 1 if we should jump to deferreturn call
|
|
p := gc.Prog(arm64.ACMP)
|
|
p.From.Type = obj.TYPE_CONST
|
|
p.From.Offset = 0
|
|
p.Reg = arm64.REG_R0
|
|
p = gc.Prog(arm64.ABNE)
|
|
p.To.Type = obj.TYPE_BRANCH
|
|
s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[1].Block()})
|
|
if b.Succs[0].Block() != next {
|
|
p := gc.Prog(obj.AJMP)
|
|
p.To.Type = obj.TYPE_BRANCH
|
|
s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[0].Block()})
|
|
}
|
|
|
|
case ssa.BlockExit:
|
|
gc.Prog(obj.AUNDEF) // tell plive.go that we never reach here
|
|
|
|
case ssa.BlockRet:
|
|
gc.Prog(obj.ARET)
|
|
|
|
case ssa.BlockRetJmp:
|
|
p := gc.Prog(obj.ARET)
|
|
p.To.Type = obj.TYPE_MEM
|
|
p.To.Name = obj.NAME_EXTERN
|
|
p.To.Sym = b.Aux.(*obj.LSym)
|
|
|
|
case ssa.BlockARM64EQ, ssa.BlockARM64NE,
|
|
ssa.BlockARM64LT, ssa.BlockARM64GE,
|
|
ssa.BlockARM64LE, ssa.BlockARM64GT,
|
|
ssa.BlockARM64ULT, ssa.BlockARM64UGT,
|
|
ssa.BlockARM64ULE, ssa.BlockARM64UGE,
|
|
ssa.BlockARM64Z, ssa.BlockARM64NZ,
|
|
ssa.BlockARM64ZW, ssa.BlockARM64NZW:
|
|
jmp := blockJump[b.Kind]
|
|
var p *obj.Prog
|
|
switch next {
|
|
case b.Succs[0].Block():
|
|
p = gc.Prog(jmp.invasm)
|
|
p.To.Type = obj.TYPE_BRANCH
|
|
s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[1].Block()})
|
|
case b.Succs[1].Block():
|
|
p = gc.Prog(jmp.asm)
|
|
p.To.Type = obj.TYPE_BRANCH
|
|
s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[0].Block()})
|
|
default:
|
|
p = gc.Prog(jmp.asm)
|
|
p.To.Type = obj.TYPE_BRANCH
|
|
s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[0].Block()})
|
|
q := gc.Prog(obj.AJMP)
|
|
q.To.Type = obj.TYPE_BRANCH
|
|
s.Branches = append(s.Branches, gc.Branch{P: q, B: b.Succs[1].Block()})
|
|
}
|
|
if !b.Control.Type.IsFlags() {
|
|
p.From.Type = obj.TYPE_REG
|
|
p.From.Reg = b.Control.Reg()
|
|
}
|
|
|
|
default:
|
|
b.Fatalf("branch not implemented: %s. Control: %s", b.LongString(), b.Control.LongString())
|
|
}
|
|
}
|