Commit Graph

62 Commits

Author SHA1 Message Date
Joel Sing 2d90df91a8 cmd/internal/obj/riscv: avoid obj.Prog rewriting for immediate splitting
Rather than rewriting the obj.Prog for a immediate instructions that need
splitting, generate the appropriate machine instruction sequence directly.

Change-Id: Ie90f0e2a98f97a29281e445c4c3b0c47b793ef4d
Reviewed-on: https://go-review.googlesource.com/c/go/+/344453
Trust: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Mui <cherryyz@google.com>
2021-09-04 19:33:01 +00:00
Joel Sing ba66d62b68 cmd/internal/obj/riscv: avoid obj.Prog rewriting for memory stores
Rather than rewriting the obj.Prog for a MOV pseudo-instruction targeting
a register to memory stores, generate the appropriate machine instruction
sequence directly.

Change-Id: I6eac8637e1fcb48c04d9f331cac7ae5d8cc54092
Reviewed-on: https://go-review.googlesource.com/c/go/+/344455
Trust: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Mui <cherryyz@google.com>
2021-09-04 10:59:00 +00:00
Joel Sing 5ec298d7b0 cmd/internal/obj/riscv: avoid obj.Prog rewriting for memory loads
Rather than rewriting the obj.Prog for a MOV pseudo-instruction targeting
a memory to register load, generate the appropriate machine instruction
sequence directly.

Change-Id: I4c7292ba00f576ec71d4842b6ff27a8ce6db0650
Reviewed-on: https://go-review.googlesource.com/c/go/+/344454
Trust: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Mui <cherryyz@google.com>
2021-09-04 10:58:11 +00:00
Joel Sing 0b66310924 cmd/internal/obj/riscv: avoid obj.Prog rewriting for store instructions
Rather than rewriting the obj.Prog for a store instruction, generate the
appropriate machine instruction sequence directly.

Change-Id: I026250ca3d249a1013243948a4e567b708b72d0c
Reviewed-on: https://go-review.googlesource.com/c/go/+/344452
Trust: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Run-TryBot: Cherry Mui <cherryyz@google.com>
TryBot-Result: Go Bot <gobot@golang.org>
2021-09-04 10:43:00 +00:00
Joel Sing 8a01010c26 cmd/internal/obj/riscv: avoid obj.Prog rewriting for load instructions
Rather than rewriting the obj.Prog for a load instruction, generate the
appropriate machine instruction sequence directly.

Change-Id: Iba656dbf2dff2bce02aa221d9a5cad7b7c4630d8
Reviewed-on: https://go-review.googlesource.com/c/go/+/344451
Trust: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Run-TryBot: Cherry Mui <cherryyz@google.com>
TryBot-Result: Go Bot <gobot@golang.org>
2021-09-04 10:42:46 +00:00
Joel Sing 9cb5716f00 cmd/internal/obj/riscv: avoid obj.Prog rewriting for constant loads
Rather than rewriting the obj.Prog for a MOV pseudo-instruction targeting
a constant to register load, generate the appropriate machine instruction
sequence directly.

Change-Id: I38e62f282b39be2a0a241f32280d306558d49b44
Reviewed-on: https://go-review.googlesource.com/c/go/+/344450
Trust: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Run-TryBot: Cherry Mui <cherryyz@google.com>
TryBot-Result: Go Bot <gobot@golang.org>
2021-09-04 10:42:34 +00:00
Joel Sing ab7c904bf2 cmd/internal/obj/riscv: factor out instructions for MOV pseudo-instructions
This factors out the machine instruction generation for MOV pseudo-instructions,
which will simplify further changes.

Change-Id: Ic0d2c3ae9e0881f7894af50ed45e93b0e4961632
Reviewed-on: https://go-review.googlesource.com/c/go/+/344461
Trust: Joel Sing <joel@sing.id.au>
Trust: Meng Zhuo <mzh@golangcn.org>
Run-TryBot: Joel Sing <joel@sing.id.au>
TryBot-Result: Go Bot <gobot@golang.org>
Reviewed-by: Meng Zhuo <mzh@golangcn.org>
Reviewed-by: Cherry Mui <cherryyz@google.com>
2021-09-03 05:27:58 +00:00
Ben Shi 37d4532867 cmd/internal/obj/riscv: simplify addition with constant
This CL simplifies riscv addition (add r, imm) to
(ADDI (ADDI r, imm/2), imm-imm/2) if imm is in specific ranges.
(-4096 <= imm <= -2049 or 2048 <= imm <= 4094)

There is little impact to the go1 benchmark, while the total
size of pkg/linux_riscv64 decreased by about 11KB.

Change-Id: I236eb8af3b83bb35ce9c0b318fc1d235e8ab9a4e
GitHub-Last-Rev: a2f56a0763
GitHub-Pull-Request: golang/go#48110
Reviewed-on: https://go-review.googlesource.com/c/go/+/346689
Run-TryBot: Ben Shi <powerman1st@163.com>
TryBot-Result: Go Bot <gobot@golang.org>
Reviewed-by: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: Keith Randall <khr@golang.org>
Trust: Michael Munday <mike.munday@lowrisc.org>
2021-09-02 14:35:10 +00:00
Michael Munday ea51e223c2 cmd/{asm,compile}: add fused multiply-add support on riscv64
Add support to the assembler for F[N]M{ADD,SUB}[SD] instructions.
Argument order is:

  OP RS1, RS2, RS3, RD

Also, add support for the FMA intrinsic to the compiler. Automatic
FMA matching is left to a future CL.

Change-Id: I47166c7393b2ab6bfc2e42aa8c1a8997c3a071b3
Reviewed-on: https://go-review.googlesource.com/c/go/+/293030
Trust: Michael Munday <mike.munday@lowrisc.org>
Run-TryBot: Michael Munday <mike.munday@lowrisc.org>
TryBot-Result: Go Bot <gobot@golang.org>
Reviewed-by: Joel Sing <joel@sing.id.au>
2021-09-01 21:17:04 +00:00
Joel Sing 5a687eeaf1 cmd/asm,cmd/internal/obj/riscv: add more error tests for riscv64 assembly
Add more error tests for riscv64 assembly. Also avoid a panic when one of
these error conditions is hit.

Change-Id: If5d913894facbd67f7d014eab745da77c8c66ab0
Reviewed-on: https://go-review.googlesource.com/c/go/+/344228
Trust: Joel Sing <joel@sing.id.au>
Run-TryBot: Joel Sing <joel@sing.id.au>
TryBot-Result: Go Bot <gobot@golang.org>
Reviewed-by: Meng Zhuo <mzh@golangcn.org>
2021-09-01 06:18:05 +00:00
Austin Clements 042f4cbb6f cmd/internal/obj/riscv: simplify huge frame prologue
CL 307010 for riscv64.

Some of the comments on the other prologue paths were wrong, so this
CL also fixes them up.

Change-Id: Icdca1ade3a47ae6e2467af832690d40689dbe1b6
Reviewed-on: https://go-review.googlesource.com/c/go/+/307150
Trust: Austin Clements <austin@google.com>
Run-TryBot: Austin Clements <austin@google.com>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2021-04-05 16:22:17 +00:00
Joel Sing c2d625168f cmd/compile,cmd/internal/obj/riscv: load >32-bit constants from memory for riscv64
Follow what MIPS does and load >32-bit constants from memory using two instructions,
rather than generating a four to six instruction sequence. This removes more than 2,500
instructions from the Go binary. This also makes it possible to load >32-bit constants
via a single assembly instruction, if required.

Change-Id: Ie679a0754071e6d8c52fe0d027f00eb241b3a758
Reviewed-on: https://go-review.googlesource.com/c/go/+/302609
Trust: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2021-03-18 04:17:00 +00:00
Joel Sing 0398a771d2 cmd/internal/obj/riscv: prevent constant loads that do not target registers
Check that the target of a constant load is a register and add test coverage
for this error condition. While here, rename the RISC-V testdata and tests
to be consistent with other platforms.

Change-Id: I7fd0bfcee8cf9df0597d72e65cd74a2d0bfd349a
Reviewed-on: https://go-review.googlesource.com/c/go/+/292895
Trust: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Go Bot <gobot@golang.org>
2021-02-23 09:15:50 +00:00
Russ Cox 4dd77bdc91 cmd/asm, cmd/link, runtime: introduce FuncInfo flag bits
The runtime traceback code has its own definition of which functions
mark the top frame of a stack, separate from the TOPFRAME bits that
exist in the assembly and are passed along in DWARF information.
It's error-prone and redundant to have two different sources of truth.
This CL provides the actual TOPFRAME bits to the runtime, so that
the runtime can use those bits instead of reinventing its own category.

This CL also adds a new bit, SPWRITE, which marks functions that
write directly to SP (anything but adding and subtracting constants).
Such functions must stop a traceback, because the traceback has no
way to rederive the SP on entry. Again, the runtime has its own definition
which is mostly correct, but also missing some functions. During ordinary
goroutine context switches, such functions do not appear on the stack,
so the incompleteness in the runtime usually doesn't matter.
But profiling signals can arrive at any moment, and the runtime may
crash during traceback if it attempts to unwind an SP-writing frame
and gets out-of-sync with the actual stack. The runtime contains code
to try to detect likely candidates but again it is incomplete.
Deriving the SPWRITE bit automatically from the actual assembly code
provides the complete truth, and passing it to the runtime lets the
runtime use it.

This CL is part of a stack adding windows/arm64
support (#36439), intended to land in the Go 1.17 cycle.
This CL is, however, not windows/arm64-specific.
It is cleanup meant to make the port (and future ports) easier.

Change-Id: I227f53b23ac5b3dabfcc5e8ee3f00df4e113cf58
Reviewed-on: https://go-review.googlesource.com/c/go/+/288800
Trust: Russ Cox <rsc@golang.org>
Trust: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Reviewed-by: Jason A. Donenfeld <Jason@zx2c4.com>
2021-02-19 00:02:30 +00:00
Russ Cox 6fe8981620 cmd/internal/obj/riscv: fix JMP name<>(SB)
It was being rejected. Now it isn't and can be used in the runtime.

Change-Id: I4626bf9fc2e0bc26fffb87d11bede459964324b3
Reviewed-on: https://go-review.googlesource.com/c/go/+/292129
Trust: Russ Cox <rsc@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2021-02-19 00:02:15 +00:00
Quey-Liang Kao 0433845ad1 cmd/asm, cmd/internal/obj/riscv: fix branch pseudo-instructions
Pseudo branch instructions BGT, BGTU, BLE, and BLEU implemented In
CL 226397 were translated inconsistently compared to other ones due
to the inversion of registers. For instance, while "BLT a, b" generates
"jump if a < b", "BLE a, b" generates "jump if b <= a."

This CL fixes the translation in the assembler and the tests.

Change-Id: Ia757be73e848734ca5b3a790e081f7c4f98c30f2
Reviewed-on: https://go-review.googlesource.com/c/go/+/271911
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Reviewed-by: Joel Sing <joel@sing.id.au>
Run-TryBot: Joel Sing <joel@sing.id.au>
2020-12-02 14:20:12 +00:00
fanzha02 15131caeaa cmd/internal/obj/arm64: add CASx/CASPx instructions
This patch adds support for CASx and CASPx atomic instructions.

  go syntax                 gnu syntax
CASD Rs, (Rn|RSP), Rt => cas Xs, Xt, (Xn|SP)
CASALW Rs, (Rn|RSP), Rt => casal Ws, Wt, (Xn|SP)
CASPD (Rs, Rs+1), (Rn|RSP), (Rt, Rt+1) => casp Xs, Xs+1, Xt, Xt+1, (Xn|SP)
CASPW (Rs, Rs+1), (Rn|RSP), (Rt, Rt+1) => casp Ws, Ws+1, Wt, Wt+1, (Xn|SP)

This patch changes the type of prog.RestArgs from "[]Addr" to
"[]struct{Addr, Pos}", Pos is a enum, indicating the position of
the operand.

This patch also adds test cases.

Change-Id: Ib971cfda7890b7aa895d17bab22dea326c7fcaa4
Reviewed-on: https://go-review.googlesource.com/c/go/+/233277
Trust: fannie zhang <Fannie.Zhang@arm.com>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-10-29 05:07:11 +00:00
Michał Derkacz 150d2448e5 cmd/compile,cmd/internal/obj/riscv,runtime: use Duff's devices on riscv64
Implement runtime.duffzero and runtime.duffcopy for riscv64.
Use obj.ADUFFZERO/obj.ADUFFCOPY for medium size, word aligned
zeroing/moving.

Change-Id: I42ec622055630c94cb77e286d8d33dbe7c9f846c
Reviewed-on: https://go-review.googlesource.com/c/go/+/237797
Run-TryBot: Cherry Zhang <cherryyz@google.com>
Reviewed-by: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-10-28 05:02:44 +00:00
Joel Sing 3a63d04d2e cmd/link,cmd/internal/obj/riscv: add TLS support for linux/riscv64
Add support for Thread Local Storage (TLS) for linux/riscv64 with external
linking, using the initial-exec model.

Update #36641

Change-Id: I3106ef9a29cde73215830b00deff43dbec1c76e0
Reviewed-on: https://go-review.googlesource.com/c/go/+/263478
Trust: Joel Sing <joel@sing.id.au>
Run-TryBot: Joel Sing <joel@sing.id.au>
TryBot-Result: Go Bot <gobot@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-10-27 04:20:42 +00:00
Joel Sing 4a67825628 cmd/internal/obj/riscv: support additional register to register moves
Add support for signed and unsigned register to register moves of various
sizes. This makes it easier to handle zero and sign extension and will allow
for further changes that improve the compiler optimisations for riscv64.

While here, change the existing register to register moves from obj.Prog
rewriting to instruction generation.

Change-Id: Id21911019b76922367a134da13c3449a84a1fb08
Reviewed-on: https://go-review.googlesource.com/c/go/+/264657
Trust: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-10-24 08:12:11 +00:00
Russ Cox 912262b806 cmd/internal/obj: move LSym.Func into LSym.Extra
This creates space for a different kind of extension field
in LSym without making the struct any larger.
(There are many LSym, so we care about keeping the struct small.)

Change-Id: Ib16edb9e15f54c2a7351c8b875e19684058711e5
Reviewed-on: https://go-review.googlesource.com/c/go/+/243943
Trust: Russ Cox <rsc@golang.org>
Run-TryBot: Russ Cox <rsc@golang.org>
TryBot-Result: Go Bot <gobot@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-10-16 03:02:36 +00:00
Joel Sing 0dde60a5fe cmd/internal/obj/riscv: clean up lowerJALR
This cleans up the last of the direct obj.Prog rewriting, removing lowerJALR
and replacing it with correct handling for AJALR during instruction encoding.

Change-Id: Ieea125bde30d4c0edd2d9ed1e50160543aa8f330
Reviewed-on: https://go-review.googlesource.com/c/go/+/249077
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Go Bot <gobot@golang.org>
Trust: Joel Sing <joel@sing.id.au>
2020-09-17 08:21:04 +00:00
Keith Randall 9e70564f63 cmd/compile,cmd/asm: simplify recording of branch targets, take 2
We currently use two fields to store the targets of branches.
Some phases use p.To.Val, some use p.Pcond. Rewrite so that
every branch instruction uses p.To.Val.
p.From.Val is also used in rare instances.
Introduce a Pool link for use by arm/arm64, instead of
repurposing Pcond.

This is a cleanup CL in preparation for some stack frame CLs.

Change-Id: If8239177e4b1ea2bccd0608eb39553d23210d405
Reviewed-on: https://go-review.googlesource.com/c/go/+/251437
Run-TryBot: Keith Randall <khr@golang.org>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-08-31 17:36:08 +00:00
Keith Randall 26ad27bb02 Revert "cmd/compile,cmd/asm: simplify recording of branch targets"
This reverts CL 243318.

Reason for revert: Seems to be crashing some builders.

Change-Id: I2ffc59bc5535be60b884b281c8d0eff4647dc756
Reviewed-on: https://go-review.googlesource.com/c/go/+/251169
Reviewed-by: Bryan C. Mills <bcmills@google.com>
2020-08-28 02:10:13 +00:00
Keith Randall 8247da3662 cmd/compile,cmd/asm: simplify recording of branch targets
We currently use two fields to store the targets of branches.
Some phases use p.To.Val, some use p.Pcond. Rewrite so that
every branch instruction uses p.To.Val.
p.From.Val is also used in rare instances.
Introduce a Pool link for use by arm/arm64, instead of
repurposing Pcond.

This is a cleanup CL in preparation for some stack frame CLs.

Change-Id: I9055bf0a1d986aff421e47951a1dedc301c846f8
Reviewed-on: https://go-review.googlesource.com/c/go/+/243318
Run-TryBot: Keith Randall <khr@golang.org>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-08-27 22:35:45 +00:00
Cherry Zhang ee330385ca cmd/internal/obj, runtime: preempt & restart some instruction sequences
On some architectures, for async preemption the injected call
needs to clobber a register (usually REGTMP) in order to return
to the preempted function. As a consequence, the PC ranges where
REGTMP is live are not preemptible.

The uses of REGTMP are usually generated by the assembler, where
it needs to load or materialize a large constant or offset that
doesn't fit into the instruction. In those cases, REGTMP is not
live at the start of the instruction sequence. Instead of giving
up preemption in those cases, we could preempt it and restart the
sequence when resuming the execution. Basically, this is like
reissuing an interrupted instruction, except that here the
"instruction" is a Prog that consists of multiple machine
instructions. For this to work, we need to generate PC data to
mark the start of the Prog.

Currently this is only done for ARM64.

TODO: the split-stack function prologue is currently not async
preemptible. We could use this mechanism, preempt it and restart
at the function entry.

Change-Id: I37cb282f8e606e7ab6f67b3edfdc6063097b4bd1
Reviewed-on: https://go-review.googlesource.com/c/go/+/208126
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Austin Clements <austin@google.com>
2020-05-06 15:41:12 +00:00
Quey-Liang Kao b89f4c6720 runtime: add async preemption support on riscv64
This CL adds support of call injection and async preemption on
riscv64. We also clobbered REG_TMP for the injected call. Unsafe
points related to REG_TMP access have been marked in previous commits.

Fixes #36711.

Change-Id: I1a1df5b7fc23eaafc34a6a6448fcc3c91054496e
GitHub-Last-Rev: f6110d4707
GitHub-Pull-Request: golang/go#38146
Reviewed-on: https://go-review.googlesource.com/c/go/+/226206
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Reviewed-by: Joel Sing <joel@sing.id.au>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
2020-04-16 05:29:18 +00:00
Joel Sing a3d8c210ad cmd/asm,cmd/internal/obj/riscv: provide branch pseudo-instructions
Implement various branch pseudo-instructions for riscv64. These make it easier
to read/write assembly and will also make it easier for the compiler to generate
optimised code.

Change-Id: Ic31a7748c0e1495522ebecf34b440842b8d12c04
Reviewed-on: https://go-review.googlesource.com/c/go/+/226397
Run-TryBot: Cherry Zhang <cherryyz@google.com>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
2020-03-31 13:13:58 +00:00
Joel Sing 25da2ea72c cmd/internal/obj/riscv: add NEG/NEGW pseudo-instructions
Provide NEG/NEGW pseudo-instructions, which translate to SUB/SUBW with the
zero register as a source.

Change-Id: I2c1ec1e75611c234c5ee8e39390dd188f8e42bae
Reviewed-on: https://go-review.googlesource.com/c/go/+/221689
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-03-15 08:15:09 +00:00
Joel Sing dc3255391a cmd/internal/obj/riscv: add NOT pseudo-instruction
Add a NOT pseudo-instruction that translates to XORI $-1.

Change-Id: I2be4cfe2939e988cd7f8d30260b704701d78475f
Reviewed-on: https://go-review.googlesource.com/c/go/+/221688
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-03-15 08:14:24 +00:00
Joel Sing 32dbccde78 cmd/internal/obj/riscv: add FCLASSS/FCLASSD instructions
Add support for floating-point classification instructions.

Change-Id: I64463d477b3db0cca16ff7bced64f154011ef4cb
Reviewed-on: https://go-review.googlesource.com/c/go/+/220542
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-03-15 08:13:55 +00:00
Joel Sing 10635921e5 cmd/asm,cmd/internal/obj/riscv: add atomic memory operation instructions
Use instructions in place of currently used defines.

Updates #36765

Change-Id: I00bb59e77b1aace549d7857cc9721ba2cb4ac6ca
Reviewed-on: https://go-review.googlesource.com/c/go/+/220541
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-03-15 08:13:28 +00:00
Joel Sing 85a8526a7e cmd/asm,cmd/internal/obj/riscv: add LR/SC instructions
Add support for Load-Reserved (LR) and Store-Conditional (SC) instructions.

Use instructions in place of currently used defines.

Updates #36765

Change-Id: I77e660639802293ece40cfde4865ac237e3308d6
Reviewed-on: https://go-review.googlesource.com/c/go/+/220540
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-03-15 07:51:41 +00:00
Joel Sing 2a08f3c181 cmd/internal/obj/riscv: add FENCE instruction
Also remove #define's that were previously in use.

Updates #36765

Change-Id: I90b6a8629c78f549012f3f6c5f3b325336182712
Reviewed-on: https://go-review.googlesource.com/c/go/+/220539
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-03-15 07:13:18 +00:00
Joel Sing 3e00061f52 cmd/internal/obj/riscv: rework instruction generation
Rework instruction generation so that multiple instructions are generated
from a single obj.Prog, rather than the current approach where obj.Progs
are rewritten. This allows the original obj.Prog to remain intact, before
being converted into an architecture specific instruction form.

This simplifies the code and removes a level of indirection that results
from trying to manipulate obj.Prog.To/obj.Prog.From into forms that match
the instruction encoding. Furthermore, the errors reported make more sense
since it matches up with the actual assembly that was parsed.

Note that the CALL/JMP/JALR type sequences have not yet been migrated to
this framework and will likely be converted at a later time.

Updates #27532

Change-Id: I9fd12562ed1db0a08cfdc32793897d2a1920ebaa
Reviewed-on: https://go-review.googlesource.com/c/go/+/211917
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
2020-03-15 06:42:43 +00:00
Joel Sing 2b920cba8f cmd/internal/obj/riscv: store relocation details in obj.Prog.RestArgs
Store the relocation offset and symbol in obj.Prog.RestArgs, rather than
overloading obj.Prog.From and having to deal with invalid offsets
potentially existing when the instruction is encoded.

Change-Id: Iff0d678361677e78b41b887f6eba08cee94fccb3
Reviewed-on: https://go-review.googlesource.com/c/go/+/218197
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
2020-03-15 06:17:36 +00:00
Russ Cox fc8a6336d1 cmd/asm, cmd/compile, runtime: add -spectre=ret mode
This commit extends the -spectre flag to cmd/asm and adds
a new Spectre mitigation mode "ret", which enables the use
of retpolines.

Retpolines prevent speculation about the target of an indirect
jump or call and are described in more detail here:
https://support.google.com/faqs/answer/7625886

Change-Id: I4f2cb982fa94e44d91e49bd98974fd125619c93a
Reviewed-on: https://go-review.googlesource.com/c/go/+/222661
Reviewed-by: Keith Randall <khr@golang.org>
2020-03-13 19:05:54 +00:00
Joel Sing a50c3ffbd4 cmd/internal/obj/riscv,cmd/link: shorten the riscv64 call sequence
Now that the other dependent offset has been identified, we can remove the
unnecessary ADDI instruction from the riscv64 call sequence (reducing it
to AUIPC+JALR, rather than the previous AUIPC+ADDI+JALR).

Change-Id: I348c4efb686f9f71ed1dd1d25fb9142a41230b0d
Reviewed-on: https://go-review.googlesource.com/c/go/+/216798
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
2020-01-29 16:35:37 +00:00
Joel Sing d8e052667f cmd/internal/obj/riscv: use signed immediates for U-instructions
On RISCV64, the U-instructions (AUIPC and LUI) take 20 bits, append 12 bits
of zeros and sign extend to 64-bits. As such, the 20 bit immediate value is
signed not unsigned.

Updates #27532

Change-Id: I725215a1dc500106dbfdc0a4425f3c0b2a6f411e
Reviewed-on: https://go-review.googlesource.com/c/go/+/216257
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-01-28 02:39:28 +00:00
Joel Sing 9f07cdd99e cmd/internal/obj/riscv: restore the ADDI instruction in jalrToSym
While this instruction is not needed for the relocation (the lower immediate
can be patched directly into the JALR instruction), other code currently
depends on the jump sequence being 12 bytes (or three instructions) long.
Put the ADDI instruction back until these can be found and fixed.

Updates #27532

Change-Id: Idb73d716be8eb2eb796591b30f1ec4dc104f2bf8
Reviewed-on: https://go-review.googlesource.com/c/go/+/215840
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
2020-01-23 07:39:53 +00:00
Joel Sing fa610c776e cmd/internal/obj/riscv: add missing instructions to the ternary expansion list
Updates #27532

Change-Id: I5beb7941c204755948350b181c713b046bc4f1f1
Reviewed-on: https://go-review.googlesource.com/c/go/+/215841
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
2020-01-23 07:33:33 +00:00
Joel Sing 6718cb617f cmd/internal/obj/riscv: implement prologue and epilogue
Based on riscv-go port.

Updates #27532

Change-Id: If552225552bf8d27c29b08de31146dd34986a3a1
Reviewed-on: https://go-review.googlesource.com/c/go/+/204630
Run-TryBot: Joel Sing <joel@sing.id.au>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-01-22 15:24:05 +00:00
Joel Sing fb8cdb7e4b cmd/internal/obj/riscv: populate DWARF register mapping for riscv64
Updates #27532

Change-Id: If147242c45d5c2d5cdc5b0428db32eeec13a958a
Reviewed-on: https://go-review.googlesource.com/c/go/+/215377
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
2020-01-21 23:58:54 +00:00
Joel Sing 1424889921 cmd/internal/obj/riscv: correctly split immediates for FLW/FLD/FSW/FSD
The FLW/FLD/FSW/FSD instructions can have immediates that exceed 12-bits and
therefore cannot be encoded in the RISCV instruction. Handle these as we do
for other load/store instructions. Also add test coverage for all load/store
instructions with large immediates.

Fixes compilation issue reported by Carlos Eduardo de Paula.

Updates #27532

Change-Id: Ifa62f19493b3acaba5a90ac31d2df209a3afea81
Reviewed-on: https://go-review.googlesource.com/c/go/+/215037
Reviewed-by: Carlos Eduardo de Paula <me@carlosedp.com>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
2020-01-21 23:58:09 +00:00
Joel Sing 98d2717499 cmd/compile: implement compiler for riscv64
Based on riscv-go port.

Updates #27532

Change-Id: Ia329daa243db63ff334053b8807ea96b97ce3acf
Reviewed-on: https://go-review.googlesource.com/c/go/+/204631
Run-TryBot: Joel Sing <joel@sing.id.au>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
2020-01-18 14:41:40 +00:00
Joel Sing 3a6cd4c72d cmd/internal/obj/riscv: correct CALL reloc symbol handling
Move the CALL reloc symbol back to p.From.Sym, rather than p.To.Sym - while
p.To.Sym is the correct final location, the call to lowerJALR flips the p.To
and p.From addresses (and proves that this form of obj.Prog rewriting is not
a good idea).

Updates #27532

Change-Id: Iaf9fa24b05bda32b963f8d243401c6cd82c1355c
Reviewed-on: https://go-review.googlesource.com/c/go/+/212759
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
2020-01-04 04:11:40 +00:00
Joel Sing 24902c5be6 cmd/internal/obj/riscv: handle MOV rewrites in separate pass
Handle the rewriting of MOV pseudo-instructions in a separate pass. This allows
AMOV to be more readily used by other code, including AGETCALLERPC and ARET
implementations.

Updates #27532

Change-Id: Iea794121210048ed23ed0fb8f3c5e3cd5354a311
Reviewed-on: https://go-review.googlesource.com/c/go/+/212758
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
2020-01-04 04:10:21 +00:00
Joel Sing 48ed1e6113 cmd/internal/obj/riscv: handle AGETCALLERPC
Updates #27532

Change-Id: Ib3e44ec524ed20bbfbbaf40df22cec335460f3ef
Reviewed-on: https://go-review.googlesource.com/c/go/+/204629
Run-TryBot: Joel Sing <joel@sing.id.au>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2019-12-24 04:59:06 +00:00
Joel Sing 24f08103d2 cmd/internal/obj/riscv: handle FEQ/FNEG/SEQZ/SNEZ
Based on riscv-go port.

Updates #27532

Change-Id: I5e7f45955e1dfdb9d09cc6a4e6f3ce81216d411d
Reviewed-on: https://go-review.googlesource.com/c/go/+/204628
Reviewed-by: Cherry Zhang <cherryyz@google.com>
2019-12-24 03:50:29 +00:00
Joel Sing 7cab55dfd3 cmd/internal/obj/riscv: handle call, jmp and branch
Also provide REG_LR to more clearly define the link register.

Based on the riscv-go port.

Updates #27532

Change-Id: I0805f373682f93b3918a01c21d4ef34eb3817c75
Reviewed-on: https://go-review.googlesource.com/c/go/+/204627
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
2019-12-24 03:42:15 +00:00