mirror
/
go
mirror of https://github.com/golang/go.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

cmd/compile, cmd/internal, runtime: change the registers used by the duff device for loong64 

Add R21 to the allocatable registers, use R20 and R21 in duff
device. This CL is in preparation for subsequent regABI support.

Updates #40724

Co-authored-by: Xiaolin Zhao <zhaoxiaolin@loongson.cn>
Change-Id: If1661adc0f766925fbe74827a369797f95fa28a9
Reviewed-on: https://go-review.googlesource.com/c/go/+/521775
Reviewed-by: David Chase <drchase@google.com>
Run-TryBot: David Chase <drchase@google.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: Meidan Li <limeidan@loongson.cn>
Reviewed-by: Than McIntosh <thanm@google.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
This commit is contained in:
Guoqi Chen 2023-08-17 03:58:10 +08:00 committed by David Chase
parent 4f55a5af5e
commit f43581131e
6 changed files with 885 additions and 885 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/cmd/compile/internal/loong64/ssa.go
View File

@ -362,7 +362,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
p.To.Type = obj.TYPE_REG
p.To.Reg = v.Reg()
case ssa.OpLOONG64DUFFZERO:
// runtime.duffzero expects start address in R19
// runtime.duffzero expects start address in R20
p := s.Prog(obj.ADUFFZERO)
p.To.Type = obj.TYPE_MEM
p.To.Name = obj.NAME_EXTERN

44
src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
View File

@ -123,7 +123,7 @@ func init() {
// Common individual register masks
var (
gp = buildReg("R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31") // R1 is LR, R2 is thread pointer, R3 is stack pointer, R21-unused, R22 is g, R30 is REGTMP
gp = buildReg("R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31") // R1 is LR, R2 is thread pointer, R3 is stack pointer, R22 is g, R30 is REGTMP
gpg = gp | buildReg("g")
gpsp = gp | buildReg("SP")
gpspg = gpg | buildReg("SP")
@ -283,22 +283,22 @@ func init() {
// arg1 = mem
// auxint = offset into duffzero code to start executing
// returns mem
// R19 aka loong64.REGRT1 changed as side effect
// R20 aka loong64.REGRT1 changed as side effect
{
name: "DUFFZERO",
aux: "Int64",
argLength: 2,
reg: regInfo{
inputs: []regMask{buildReg("R19")},
clobbers: buildReg("R19 R1"),
inputs: []regMask{buildReg("R20")},
clobbers: buildReg("R20 R1"),
},
typ: "Mem",
faultOnNilArg0: true,
},
// duffcopy
// arg0 = address of dst memory (in R20, changed as side effect) REGRT2
// arg1 = address of src memory (in R19, changed as side effect) REGRT1
// arg0 = address of dst memory (in R21, changed as side effect)
// arg1 = address of src memory (in R20, changed as side effect)
// arg2 = mem
// auxint = offset into duffcopy code to start executing
// returns mem
@ -307,8 +307,8 @@ func init() {
aux: "Int64",
argLength: 3,
reg: regInfo{
inputs: []regMask{buildReg("R20"), buildReg("R19")},
clobbers: buildReg("R19 R20 R1"),
inputs: []regMask{buildReg("R21"), buildReg("R20")},
clobbers: buildReg("R20 R21 R1"),
},
typ: "Mem",
faultOnNilArg0: true,
@ -316,45 +316,45 @@ func init() {
},
// large or unaligned zeroing
// arg0 = address of memory to zero (in R19, changed as side effect)
// arg0 = address of memory to zero (in R20, changed as side effect)
// arg1 = address of the last element to zero
// arg2 = mem
// auxint = alignment
// returns mem
// MOVx R0, (R19)
// ADDV $sz, R19
// BGEU Rarg1, R19, -2(PC)
// MOVx R0, (R20)
// ADDV $sz, R20
// BGEU Rarg1, R20, -2(PC)
{
name: "LoweredZero",
aux: "Int64",
argLength: 3,
reg: regInfo{
inputs: []regMask{buildReg("R19"), gp},
clobbers: buildReg("R19"),
inputs: []regMask{buildReg("R20"), gp},
clobbers: buildReg("R20"),
},
typ: "Mem",
faultOnNilArg0: true,
},
// large or unaligned move
// arg0 = address of dst memory (in R20, changed as side effect)
// arg1 = address of src memory (in R19, changed as side effect)
// arg0 = address of dst memory (in R21, changed as side effect)
// arg1 = address of src memory (in R20, changed as side effect)
// arg2 = address of the last element of src
// arg3 = mem
// auxint = alignment
// returns mem
// MOVx (R19), Rtmp
// MOVx Rtmp, (R20)
// ADDV $sz, R19
// MOVx (R20), Rtmp
// MOVx Rtmp, (R21)
// ADDV $sz, R20
// BGEU Rarg2, R19, -4(PC)
// ADDV $sz, R21
// BGEU Rarg2, R20, -4(PC)
{
name: "LoweredMove",
aux: "Int64",
argLength: 4,
reg: regInfo{
inputs: []regMask{buildReg("R20"), buildReg("R19"), gp},
clobbers: buildReg("R19 R20"),
inputs: []regMask{buildReg("R21"), buildReg("R20"), gp},
clobbers: buildReg("R20 R21"),
},
typ: "Mem",
faultOnNilArg0: true,

426
src/cmd/compile/internal/ssa/opGen.go
View File

File diff suppressed because it is too large Load Diff

8
src/cmd/internal/obj/loong64/a.out.go
View File

@ -157,14 +157,14 @@ const (
REGZERO = REG_R0 // set to zero
REGLINK = REG_R1
REGSP = REG_R3
REGRET = REG_R19
REGRET = REG_R20 // not use
REGARG = -1 // -1 disables passing the first argument in register
REGRT1 = REG_R19 // reserved for runtime, duffzero and duffcopy
REGRT2 = REG_R20 // reserved for runtime, duffcopy
REGRT1 = REG_R20 // reserved for runtime, duffzero and duffcopy
REGRT2 = REG_R21 // reserved for runtime, duffcopy
REGCTXT = REG_R29 // context for closures
REGG = REG_R22 // G in loong64
REGTMP = REG_R30 // used by the assembler
FREGRET = REG_F0
FREGRET = REG_F0 // not use
)
var LOONG64DWARFRegisters = map[int16]int16{}

1280
src/runtime/duff_loong64.s
View File

File diff suppressed because it is too large Load Diff

10
src/runtime/mkduff.go
View File

@ -183,8 +183,8 @@ func zeroLOONG64(w io.Writer) {
// On return, R19 points to the last zeroed dword.
fmt.Fprintln(w, "TEXT runtime·duffzero(SB), NOSPLIT|NOFRAME, $0-0")
for i := 0; i < 128; i++ {
fmt.Fprintln(w, "\tMOVV\tR0, (R19)")
fmt.Fprintln(w, "\tADDV\t$8, R19")
fmt.Fprintln(w, "\tMOVV\tR0, (R20)")
fmt.Fprintln(w, "\tADDV\t$8, R20")
}
fmt.Fprintln(w, "\tRET")
}
@ -192,10 +192,10 @@ func zeroLOONG64(w io.Writer) {
func copyLOONG64(w io.Writer) {
fmt.Fprintln(w, "TEXT runtime·duffcopy(SB), NOSPLIT|NOFRAME, $0-0")
for i := 0; i < 128; i++ {
fmt.Fprintln(w, "\tMOVV\t(R19), R30")
fmt.Fprintln(w, "\tADDV\t$8, R19")
fmt.Fprintln(w, "\tMOVV\tR30, (R20)")
fmt.Fprintln(w, "\tMOVV\t(R20), R30")
fmt.Fprintln(w, "\tADDV\t$8, R20")
fmt.Fprintln(w, "\tMOVV\tR30, (R21)")
fmt.Fprintln(w, "\tADDV\t$8, R21")
fmt.Fprintln(w)
}
fmt.Fprintln(w, "\tRET")