mirror of https://github.com/golang/go.git
cmd/internal/asm/ppc64: support 34b ADD/MOVD $const, Rx
For constant signed values which require 34b to represent, the assembler will generate a pli instruction on linux/power10/PPC64 instead of loading a constant. Similarly, ADD is extended to support 34b signed constants. On linux/power10/PPC64, this generates a paddi instruction. For assembler consistency, a second form is added if paddi cannot be used. The second form is provided for assembly writers. Change-Id: I98144306af766b02fbbe36b72856a23cdf51d247 Reviewed-on: https://go-review.googlesource.com/c/go/+/528317 TryBot-Result: Gopher Robot <gobot@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Eli Bendersky <eliben@google.com> Run-TryBot: Paul Murphy <murp@ibm.com> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com>
This commit is contained in:
Paul E. Murphy
Paul Murphy
parent
6bcf176829
commit
e9379a8f8b
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@ -33,6 +33,10 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
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MOVD $2147483649, R5 // 6405800060a50001 or 0600800038a00001
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// Hex constant 0xFFFFFFFF80000001
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MOVD $-2147483647, R5 // 3ca0800060a50001 or 0603800038a00001
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// Hex constant 0xFFFFFFFE00000000 (load of constant on < power10, pli on >= power10
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MOVD $-8589934592, R5 // 3ca00000e8a50000 or 0602000038a00000
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// Hex constant 0xFFFFFFFE00000000
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ADD $-8589934592, R5 // 3fe0fffe63ff00007bff83e463ff00007cbf2a14 or 0602000038a50000
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MOVD 8(R3), R4 // e8830008
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MOVD (R3)(R4), R5 // 7ca4182a
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MOVD (R3)(R0), R5 // 7ca0182a
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@ -545,7 +545,7 @@ type PrefixableOptab struct {
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//
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// This requires an ISA 3.1 compatible cpu (e.g Power10), and when linking externally an ELFv2 1.5 compliant.
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var prefixableOptab = []PrefixableOptab{
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{Optab: Optab{as: AMOVD, a1: C_LCON, a6: C_REG, type_: 19, size: 8}, minGOPPC64: 10, pfxsize: 8},
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{Optab: Optab{as: AMOVD, a1: C_S34CON, a6: C_REG, type_: 19, size: 8}, minGOPPC64: 10, pfxsize: 8},
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{Optab: Optab{as: AMOVD, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
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{Optab: Optab{as: AMOVD, a1: C_TLS_LE, a6: C_REG, type_: 79, size: 8}, minGOPPC64: 10, pfxsize: 8},
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{Optab: Optab{as: AMOVD, a1: C_TLS_IE, a6: C_REG, type_: 80, size: 12}, minGOPPC64: 10, pfxsize: 12},
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@ -578,6 +578,8 @@ var prefixableOptab = []PrefixableOptab{
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{Optab: Optab{as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 22, size: 12}, minGOPPC64: 10, pfxsize: 8},
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{Optab: Optab{as: AADD, a1: C_LCON, a6: C_REG, type_: 22, size: 12}, minGOPPC64: 10, pfxsize: 8},
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{Optab: Optab{as: AADD, a1: C_S34CON, a2: C_REG, a6: C_REG, type_: 22, size: 20}, minGOPPC64: 10, pfxsize: 8},
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{Optab: Optab{as: AADD, a1: C_S34CON, a6: C_REG, type_: 22, size: 20}, minGOPPC64: 10, pfxsize: 8},
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}
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var oprange [ALAST & obj.AMask][]Optab
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@ -2978,7 +2980,7 @@ func asmout(c *ctxt9, p *obj.Prog, o *Optab, out *[5]uint32) {
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o1 = AOP_IRR(c.opirr(AADDIS), uint32(p.To.Reg), uint32(r), uint32(v)>>16)
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}
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case 22: /* add $lcon/$andcon,r1,r2 ==> oris+ori+add/ori+add */
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case 22: /* add $lcon/$andcon,r1,r2 ==> oris+ori+add/ori+add, add $s34con,r1 ==> addis+ori+slw+ori+add */
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if p.To.Reg == REGTMP || p.Reg == REGTMP {
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c.ctxt.Diag("can't synthesize large constant\n%v", p)
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}
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@ -2990,19 +2992,23 @@ func asmout(c *ctxt9, p *obj.Prog, o *Optab, out *[5]uint32) {
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if p.From.Sym != nil {
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c.ctxt.Diag("%v is not supported", p)
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}
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// If operand is ANDCON, generate 2 instructions using
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// ORI for unsigned value; with LCON 3 instructions.
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if o.size == 8 {
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o1 = LOP_IRR(OP_ORI, REGTMP, REGZERO, uint32(int32(d)))
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o2 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
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} else {
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o1 = loadu32(REGTMP, d)
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o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d)))
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o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
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}
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if o.ispfx {
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o1, o2 = pfxadd(int16(p.To.Reg), int16(r), PFX_R_ABS, d)
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} else if o.size == 8 {
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o1 = LOP_IRR(OP_ORI, REGTMP, REGZERO, uint32(int32(d))) // tmp = uint16(d)
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o2 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) // to = tmp + from
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} else if o.size == 12 {
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// Note, o1 is ADDIS if d is negative, ORIS otherwise.
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o1 = loadu32(REGTMP, d) // tmp = d & 0xFFFF0000
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o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) // tmp |= d & 0xFFFF
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o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) // to = from + tmp
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} else {
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// For backwards compatibility with GOPPC64 < 10, generate 34b constants in register.
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o1 = LOP_IRR(OP_ADDIS, REGZERO, REGTMP, uint32(d>>32)) // tmp = sign_extend((d>>32)&0xFFFF0000)
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o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(d>>16)) // tmp |= (d>>16)&0xFFFF
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o3 = AOP_RLDIC(OP_RLDICR, REGTMP, REGTMP, 16, 63-16) // tmp <<= 16
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o4 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(uint16(d))) // tmp |= d&0xFFFF
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o5 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
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}
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case 23: /* and $lcon/$addcon,r1,r2 ==> oris+ori+and/addi+and */
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@ -81,10 +81,14 @@ func progedit(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) {
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case AMOVD:
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// 32b constants (signed and unsigned) can be generated via 1 or 2 instructions.
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// All others must be placed in memory and loaded.
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isS32 := int64(int32(p.From.Offset)) == p.From.Offset
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isU32 := uint64(uint32(p.From.Offset)) == uint64(p.From.Offset)
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if p.From.Type == obj.TYPE_CONST && p.From.Name == obj.NAME_NONE && p.From.Reg == 0 && !isS32 && !isU32 {
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// If prefixed instructions are supported, a 34b signed constant can be generated by one pli instruction.
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isS34 := pfxEnabled && (p.From.Offset<<30)>>30 == p.From.Offset
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// If the constant cannot be generated with 2 or less instructions, it must be placed in memory and loaded.
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if p.From.Type == obj.TYPE_CONST && p.From.Name == obj.NAME_NONE && p.From.Reg == 0 && !isS32 && !isU32 && !isS34 {
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p.From.Type = obj.TYPE_MEM
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p.From.Sym = ctxt.Int64Sym(p.From.Offset)
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p.From.Name = obj.NAME_EXTERN
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