mirror of https://github.com/golang/go.git
cmd/compile: convert remaining mips rules to typed aux
Passes GOARCH=mips gotip build -toolexec 'toolstash -cmp' -a std GOARCH=mipsle gotip build -toolexec 'toolstash -cmp' -a std Change-Id: I35df0522e299aa755491cd25f47f1f1bf447848c Reviewed-on: https://go-review.googlesource.com/c/go/+/229637 Reviewed-by: Keith Randall <khr@golang.org>
This commit is contained in:
Alberto Donizetti
parent
619c7a48a3
commit
e47a17aeee
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@ -346,15 +346,15 @@
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(AtomicCompareAndSwap32 ...) => (LoweredAtomicCas ...)
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// AtomicOr8(ptr,val) -> LoweredAtomicOr(ptr&^3,uint32(val) << ((ptr & 3) * 8))
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(AtomicOr8 ptr val mem) && !config.BigEndian ->
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// AtomicOr8(ptr,val) => LoweredAtomicOr(ptr&^3,uint32(val) << ((ptr & 3) * 8))
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(AtomicOr8 ptr val mem) && !config.BigEndian =>
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(LoweredAtomicOr (AND <typ.UInt32Ptr> (MOVWconst [^3]) ptr)
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(SLL <typ.UInt32> (ZeroExt8to32 val)
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(SLLconst <typ.UInt32> [3]
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(ANDconst <typ.UInt32> [3] ptr))) mem)
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// AtomicAnd8(ptr,val) -> LoweredAtomicAnd(ptr&^3,(uint32(val) << ((ptr & 3) * 8)) | ^(uint32(0xFF) << ((ptr & 3) * 8))))
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(AtomicAnd8 ptr val mem) && !config.BigEndian ->
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// AtomicAnd8(ptr,val) => LoweredAtomicAnd(ptr&^3,(uint32(val) << ((ptr & 3) * 8)) | ^(uint32(0xFF) << ((ptr & 3) * 8))))
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(AtomicAnd8 ptr val mem) && !config.BigEndian =>
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(LoweredAtomicAnd (AND <typ.UInt32Ptr> (MOVWconst [^3]) ptr)
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(OR <typ.UInt32> (SLL <typ.UInt32> (ZeroExt8to32 val)
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(SLLconst <typ.UInt32> [3]
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@ -363,16 +363,16 @@
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(MOVWconst [0xff]) (SLLconst <typ.UInt32> [3]
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(ANDconst <typ.UInt32> [3] ptr))))) mem)
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// AtomicOr8(ptr,val) -> LoweredAtomicOr(ptr&^3,uint32(val) << (((ptr^3) & 3) * 8))
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(AtomicOr8 ptr val mem) && config.BigEndian ->
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// AtomicOr8(ptr,val) => LoweredAtomicOr(ptr&^3,uint32(val) << (((ptr^3) & 3) * 8))
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(AtomicOr8 ptr val mem) && config.BigEndian =>
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(LoweredAtomicOr (AND <typ.UInt32Ptr> (MOVWconst [^3]) ptr)
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(SLL <typ.UInt32> (ZeroExt8to32 val)
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(SLLconst <typ.UInt32> [3]
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(ANDconst <typ.UInt32> [3]
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(XORconst <typ.UInt32> [3] ptr)))) mem)
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// AtomicAnd8(ptr,val) -> LoweredAtomicAnd(ptr&^3,(uint32(val) << (((ptr^3) & 3) * 8)) | ^(uint32(0xFF) << (((ptr^3) & 3) * 8))))
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(AtomicAnd8 ptr val mem) && config.BigEndian ->
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// AtomicAnd8(ptr,val) => LoweredAtomicAnd(ptr&^3,(uint32(val) << (((ptr^3) & 3) * 8)) | ^(uint32(0xFF) << (((ptr^3) & 3) * 8))))
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(AtomicAnd8 ptr val mem) && config.BigEndian =>
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(LoweredAtomicAnd (AND <typ.UInt32Ptr> (MOVWconst [^3]) ptr)
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(OR <typ.UInt32> (SLL <typ.UInt32> (ZeroExt8to32 val)
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(SLLconst <typ.UInt32> [3]
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@ -385,142 +385,142 @@
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// checks
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(NilCheck ...) -> (LoweredNilCheck ...)
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(IsNonNil ptr) -> (SGTU ptr (MOVWconst [0]))
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(IsInBounds idx len) -> (SGTU len idx)
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(IsSliceInBounds idx len) -> (XORconst [1] (SGTU idx len))
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(NilCheck ...) => (LoweredNilCheck ...)
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(IsNonNil ptr) => (SGTU ptr (MOVWconst [0]))
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(IsInBounds idx len) => (SGTU len idx)
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(IsSliceInBounds idx len) => (XORconst [1] (SGTU idx len))
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// pseudo-ops
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(GetClosurePtr ...) -> (LoweredGetClosurePtr ...)
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(GetCallerSP ...) -> (LoweredGetCallerSP ...)
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(GetCallerPC ...) -> (LoweredGetCallerPC ...)
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(GetClosurePtr ...) => (LoweredGetClosurePtr ...)
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(GetCallerSP ...) => (LoweredGetCallerSP ...)
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(GetCallerPC ...) => (LoweredGetCallerPC ...)
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(If cond yes no) -> (NE cond yes no)
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(If cond yes no) => (NE cond yes no)
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// Write barrier.
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(WB ...) -> (LoweredWB ...)
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(WB ...) => (LoweredWB ...)
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(PanicBounds [kind] x y mem) && boundsABI(kind) == 0 -> (LoweredPanicBoundsA [kind] x y mem)
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(PanicBounds [kind] x y mem) && boundsABI(kind) == 1 -> (LoweredPanicBoundsB [kind] x y mem)
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(PanicBounds [kind] x y mem) && boundsABI(kind) == 2 -> (LoweredPanicBoundsC [kind] x y mem)
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(PanicBounds [kind] x y mem) && boundsABI(kind) == 0 => (LoweredPanicBoundsA [kind] x y mem)
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(PanicBounds [kind] x y mem) && boundsABI(kind) == 1 => (LoweredPanicBoundsB [kind] x y mem)
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(PanicBounds [kind] x y mem) && boundsABI(kind) == 2 => (LoweredPanicBoundsC [kind] x y mem)
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(PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 0 -> (LoweredPanicExtendA [kind] hi lo y mem)
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(PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 1 -> (LoweredPanicExtendB [kind] hi lo y mem)
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(PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 2 -> (LoweredPanicExtendC [kind] hi lo y mem)
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(PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 0 => (LoweredPanicExtendA [kind] hi lo y mem)
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(PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 1 => (LoweredPanicExtendB [kind] hi lo y mem)
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(PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 2 => (LoweredPanicExtendC [kind] hi lo y mem)
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// Optimizations
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// Absorb boolean tests into block
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(NE (FPFlagTrue cmp) yes no) -> (FPT cmp yes no)
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(NE (FPFlagFalse cmp) yes no) -> (FPF cmp yes no)
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(EQ (FPFlagTrue cmp) yes no) -> (FPF cmp yes no)
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(EQ (FPFlagFalse cmp) yes no) -> (FPT cmp yes no)
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(NE (XORconst [1] cmp:(SGT _ _)) yes no) -> (EQ cmp yes no)
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(NE (XORconst [1] cmp:(SGTU _ _)) yes no) -> (EQ cmp yes no)
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(NE (XORconst [1] cmp:(SGTconst _)) yes no) -> (EQ cmp yes no)
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(NE (XORconst [1] cmp:(SGTUconst _)) yes no) -> (EQ cmp yes no)
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(NE (XORconst [1] cmp:(SGTzero _)) yes no) -> (EQ cmp yes no)
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(NE (XORconst [1] cmp:(SGTUzero _)) yes no) -> (EQ cmp yes no)
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(EQ (XORconst [1] cmp:(SGT _ _)) yes no) -> (NE cmp yes no)
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(EQ (XORconst [1] cmp:(SGTU _ _)) yes no) -> (NE cmp yes no)
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(EQ (XORconst [1] cmp:(SGTconst _)) yes no) -> (NE cmp yes no)
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(EQ (XORconst [1] cmp:(SGTUconst _)) yes no) -> (NE cmp yes no)
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(EQ (XORconst [1] cmp:(SGTzero _)) yes no) -> (NE cmp yes no)
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(EQ (XORconst [1] cmp:(SGTUzero _)) yes no) -> (NE cmp yes no)
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(NE (SGTUconst [1] x) yes no) -> (EQ x yes no)
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(EQ (SGTUconst [1] x) yes no) -> (NE x yes no)
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(NE (SGTUzero x) yes no) -> (NE x yes no)
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(EQ (SGTUzero x) yes no) -> (EQ x yes no)
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(NE (SGTconst [0] x) yes no) -> (LTZ x yes no)
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(EQ (SGTconst [0] x) yes no) -> (GEZ x yes no)
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(NE (SGTzero x) yes no) -> (GTZ x yes no)
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(EQ (SGTzero x) yes no) -> (LEZ x yes no)
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(NE (FPFlagTrue cmp) yes no) => (FPT cmp yes no)
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(NE (FPFlagFalse cmp) yes no) => (FPF cmp yes no)
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(EQ (FPFlagTrue cmp) yes no) => (FPF cmp yes no)
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(EQ (FPFlagFalse cmp) yes no) => (FPT cmp yes no)
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(NE (XORconst [1] cmp:(SGT _ _)) yes no) => (EQ cmp yes no)
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(NE (XORconst [1] cmp:(SGTU _ _)) yes no) => (EQ cmp yes no)
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(NE (XORconst [1] cmp:(SGTconst _)) yes no) => (EQ cmp yes no)
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(NE (XORconst [1] cmp:(SGTUconst _)) yes no) => (EQ cmp yes no)
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(NE (XORconst [1] cmp:(SGTzero _)) yes no) => (EQ cmp yes no)
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(NE (XORconst [1] cmp:(SGTUzero _)) yes no) => (EQ cmp yes no)
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(EQ (XORconst [1] cmp:(SGT _ _)) yes no) => (NE cmp yes no)
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(EQ (XORconst [1] cmp:(SGTU _ _)) yes no) => (NE cmp yes no)
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(EQ (XORconst [1] cmp:(SGTconst _)) yes no) => (NE cmp yes no)
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(EQ (XORconst [1] cmp:(SGTUconst _)) yes no) => (NE cmp yes no)
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(EQ (XORconst [1] cmp:(SGTzero _)) yes no) => (NE cmp yes no)
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(EQ (XORconst [1] cmp:(SGTUzero _)) yes no) => (NE cmp yes no)
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(NE (SGTUconst [1] x) yes no) => (EQ x yes no)
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(EQ (SGTUconst [1] x) yes no) => (NE x yes no)
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(NE (SGTUzero x) yes no) => (NE x yes no)
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(EQ (SGTUzero x) yes no) => (EQ x yes no)
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(NE (SGTconst [0] x) yes no) => (LTZ x yes no)
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(EQ (SGTconst [0] x) yes no) => (GEZ x yes no)
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(NE (SGTzero x) yes no) => (GTZ x yes no)
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(EQ (SGTzero x) yes no) => (LEZ x yes no)
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// fold offset into address
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(ADDconst [off1] (MOVWaddr [off2] {sym} ptr)) -> (MOVWaddr [off1+off2] {sym} ptr)
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(ADDconst [off1] (MOVWaddr [off2] {sym} ptr)) => (MOVWaddr [off1+off2] {sym} ptr)
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// fold address into load/store
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(MOVBload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVBload [off1+off2] {sym} ptr mem)
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(MOVBUload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVBUload [off1+off2] {sym} ptr mem)
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(MOVHload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVHload [off1+off2] {sym} ptr mem)
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(MOVHUload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVHUload [off1+off2] {sym} ptr mem)
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(MOVWload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVWload [off1+off2] {sym} ptr mem)
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(MOVFload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVFload [off1+off2] {sym} ptr mem)
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(MOVDload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVDload [off1+off2] {sym} ptr mem)
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(MOVBload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVBload [off1+off2] {sym} ptr mem)
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(MOVBUload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVBUload [off1+off2] {sym} ptr mem)
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(MOVHload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVHload [off1+off2] {sym} ptr mem)
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(MOVHUload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVHUload [off1+off2] {sym} ptr mem)
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(MOVWload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVWload [off1+off2] {sym} ptr mem)
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(MOVFload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVFload [off1+off2] {sym} ptr mem)
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(MOVDload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVDload [off1+off2] {sym} ptr mem)
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(MOVBstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVBstore [off1+off2] {sym} ptr val mem)
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(MOVHstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVHstore [off1+off2] {sym} ptr val mem)
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(MOVWstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVWstore [off1+off2] {sym} ptr val mem)
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(MOVFstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVFstore [off1+off2] {sym} ptr val mem)
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(MOVDstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVDstore [off1+off2] {sym} ptr val mem)
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(MOVBstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVBstore [off1+off2] {sym} ptr val mem)
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(MOVHstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVHstore [off1+off2] {sym} ptr val mem)
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(MOVWstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVWstore [off1+off2] {sym} ptr val mem)
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(MOVFstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVFstore [off1+off2] {sym} ptr val mem)
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(MOVDstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVDstore [off1+off2] {sym} ptr val mem)
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(MOVBstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVBstorezero [off1+off2] {sym} ptr mem)
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(MOVHstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVHstorezero [off1+off2] {sym} ptr mem)
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(MOVWstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVWstorezero [off1+off2] {sym} ptr mem)
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(MOVBstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVBstorezero [off1+off2] {sym} ptr mem)
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(MOVHstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVHstorezero [off1+off2] {sym} ptr mem)
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(MOVWstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVWstorezero [off1+off2] {sym} ptr mem)
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(MOVBload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
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(MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVBUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
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(MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVHload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
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(MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVHUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
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(MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVWload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
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(MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVFload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
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(MOVFload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVDload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
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(MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVBload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
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(MOVBload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
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(MOVBUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
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(MOVBUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
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(MOVHload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
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(MOVHload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
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(MOVHUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
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(MOVHUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
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(MOVWload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
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(MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
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(MOVFload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
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(MOVFload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
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(MOVDload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
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(MOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
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(MOVBstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
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(MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
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(MOVHstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
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(MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
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(MOVWstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
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(MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
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(MOVFstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
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(MOVFstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
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(MOVDstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
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(MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
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(MOVBstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
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(MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
||||
(MOVHstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
|
||||
(MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
||||
(MOVWstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
|
||||
(MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
||||
(MOVBstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
|
||||
(MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
|
||||
(MOVHstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
|
||||
(MOVHstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
|
||||
(MOVWstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
|
||||
(MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
|
||||
(MOVFstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
|
||||
(MOVFstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
|
||||
(MOVDstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
|
||||
(MOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
|
||||
(MOVBstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
|
||||
(MOVBstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
|
||||
(MOVHstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
|
||||
(MOVHstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
|
||||
(MOVWstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
|
||||
(MOVWstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
|
||||
|
||||
// replace load from same location as preceding store with zero/sign extension (or copy in case of full width)
|
||||
(MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVBreg x)
|
||||
(MOVBUload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVBUreg x)
|
||||
(MOVHload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVHreg x)
|
||||
(MOVHUload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVHUreg x)
|
||||
(MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x
|
||||
(MOVFload [off] {sym} ptr (MOVFstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x
|
||||
(MOVDload [off] {sym} ptr (MOVDstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x
|
||||
(MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBreg x)
|
||||
(MOVBUload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBUreg x)
|
||||
(MOVHload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVHreg x)
|
||||
(MOVHUload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVHUreg x)
|
||||
(MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => x
|
||||
(MOVFload [off] {sym} ptr (MOVFstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => x
|
||||
(MOVDload [off] {sym} ptr (MOVDstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => x
|
||||
|
||||
// store zero
|
||||
(MOVBstore [off] {sym} ptr (MOVWconst [0]) mem) -> (MOVBstorezero [off] {sym} ptr mem)
|
||||
(MOVHstore [off] {sym} ptr (MOVWconst [0]) mem) -> (MOVHstorezero [off] {sym} ptr mem)
|
||||
(MOVWstore [off] {sym} ptr (MOVWconst [0]) mem) -> (MOVWstorezero [off] {sym} ptr mem)
|
||||
(MOVBstore [off] {sym} ptr (MOVWconst [0]) mem) => (MOVBstorezero [off] {sym} ptr mem)
|
||||
(MOVHstore [off] {sym} ptr (MOVWconst [0]) mem) => (MOVHstorezero [off] {sym} ptr mem)
|
||||
(MOVWstore [off] {sym} ptr (MOVWconst [0]) mem) => (MOVWstorezero [off] {sym} ptr mem)
|
||||
|
||||
// don't extend after proper load
|
||||
(MOVBreg x:(MOVBload _ _)) -> (MOVWreg x)
|
||||
(MOVBUreg x:(MOVBUload _ _)) -> (MOVWreg x)
|
||||
(MOVHreg x:(MOVBload _ _)) -> (MOVWreg x)
|
||||
(MOVHreg x:(MOVBUload _ _)) -> (MOVWreg x)
|
||||
(MOVHreg x:(MOVHload _ _)) -> (MOVWreg x)
|
||||
(MOVHUreg x:(MOVBUload _ _)) -> (MOVWreg x)
|
||||
(MOVHUreg x:(MOVHUload _ _)) -> (MOVWreg x)
|
||||
(MOVBreg x:(MOVBload _ _)) => (MOVWreg x)
|
||||
(MOVBUreg x:(MOVBUload _ _)) => (MOVWreg x)
|
||||
(MOVHreg x:(MOVBload _ _)) => (MOVWreg x)
|
||||
(MOVHreg x:(MOVBUload _ _)) => (MOVWreg x)
|
||||
(MOVHreg x:(MOVHload _ _)) => (MOVWreg x)
|
||||
(MOVHUreg x:(MOVBUload _ _)) => (MOVWreg x)
|
||||
(MOVHUreg x:(MOVHUload _ _)) => (MOVWreg x)
|
||||
|
||||
// fold double extensions
|
||||
(MOVBreg x:(MOVBreg _)) -> (MOVWreg x)
|
||||
(MOVBUreg x:(MOVBUreg _)) -> (MOVWreg x)
|
||||
(MOVHreg x:(MOVBreg _)) -> (MOVWreg x)
|
||||
(MOVHreg x:(MOVBUreg _)) -> (MOVWreg x)
|
||||
(MOVHreg x:(MOVHreg _)) -> (MOVWreg x)
|
||||
(MOVHUreg x:(MOVBUreg _)) -> (MOVWreg x)
|
||||
(MOVHUreg x:(MOVHUreg _)) -> (MOVWreg x)
|
||||
(MOVBreg x:(MOVBreg _)) => (MOVWreg x)
|
||||
(MOVBUreg x:(MOVBUreg _)) => (MOVWreg x)
|
||||
(MOVHreg x:(MOVBreg _)) => (MOVWreg x)
|
||||
(MOVHreg x:(MOVBUreg _)) => (MOVWreg x)
|
||||
(MOVHreg x:(MOVHreg _)) => (MOVWreg x)
|
||||
(MOVHUreg x:(MOVBUreg _)) => (MOVWreg x)
|
||||
(MOVHUreg x:(MOVHUreg _)) => (MOVWreg x)
|
||||
|
||||
// sign extended loads
|
||||
// Note: The combined instruction must end up in the same block
|
||||
|
|
@ -530,168 +530,166 @@
|
|||
// Make sure we don't combine these ops if the load has another use.
|
||||
// This prevents a single load from being split into multiple loads
|
||||
// which then might return different values. See test/atomicload.go.
|
||||
(MOVBreg <t> x:(MOVBUload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBload <t> [off] {sym} ptr mem)
|
||||
(MOVBUreg <t> x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBUload <t> [off] {sym} ptr mem)
|
||||
(MOVHreg <t> x:(MOVHUload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHload <t> [off] {sym} ptr mem)
|
||||
(MOVHUreg <t> x:(MOVHload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHUload <t> [off] {sym} ptr mem)
|
||||
(MOVBreg <t> x:(MOVBUload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBload <t> [off] {sym} ptr mem)
|
||||
(MOVBUreg <t> x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBUload <t> [off] {sym} ptr mem)
|
||||
(MOVHreg <t> x:(MOVHUload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVHload <t> [off] {sym} ptr mem)
|
||||
(MOVHUreg <t> x:(MOVHload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVHUload <t> [off] {sym} ptr mem)
|
||||
|
||||
// fold extensions and ANDs together
|
||||
(MOVBUreg (ANDconst [c] x)) -> (ANDconst [c&0xff] x)
|
||||
(MOVHUreg (ANDconst [c] x)) -> (ANDconst [c&0xffff] x)
|
||||
(MOVBreg (ANDconst [c] x)) && c & 0x80 == 0 -> (ANDconst [c&0x7f] x)
|
||||
(MOVHreg (ANDconst [c] x)) && c & 0x8000 == 0 -> (ANDconst [c&0x7fff] x)
|
||||
(MOVBUreg (ANDconst [c] x)) => (ANDconst [c&0xff] x)
|
||||
(MOVHUreg (ANDconst [c] x)) => (ANDconst [c&0xffff] x)
|
||||
(MOVBreg (ANDconst [c] x)) && c & 0x80 == 0 => (ANDconst [c&0x7f] x)
|
||||
(MOVHreg (ANDconst [c] x)) && c & 0x8000 == 0 => (ANDconst [c&0x7fff] x)
|
||||
|
||||
// don't extend before store
|
||||
(MOVBstore [off] {sym} ptr (MOVBreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr (MOVBUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr (MOVHreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr (MOVHUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
|
||||
(MOVHstore [off] {sym} ptr (MOVHreg x) mem) -> (MOVHstore [off] {sym} ptr x mem)
|
||||
(MOVHstore [off] {sym} ptr (MOVHUreg x) mem) -> (MOVHstore [off] {sym} ptr x mem)
|
||||
(MOVHstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVHstore [off] {sym} ptr x mem)
|
||||
(MOVWstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVWstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr (MOVBUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr (MOVHreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr (MOVWreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
|
||||
(MOVHstore [off] {sym} ptr (MOVHreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
|
||||
(MOVHstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
|
||||
(MOVHstore [off] {sym} ptr (MOVWreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
|
||||
(MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
|
||||
|
||||
// if a register move has only 1 use, just use the same register without emitting instruction
|
||||
// MOVWnop doesn't emit instruction, only for ensuring the type.
|
||||
(MOVWreg x) && x.Uses == 1 -> (MOVWnop x)
|
||||
(MOVWreg x) && x.Uses == 1 => (MOVWnop x)
|
||||
|
||||
// fold constant into arithmatic ops
|
||||
(ADD x (MOVWconst [c])) -> (ADDconst [c] x)
|
||||
(SUB x (MOVWconst [c])) -> (SUBconst [c] x)
|
||||
(AND x (MOVWconst [c])) -> (ANDconst [c] x)
|
||||
(OR x (MOVWconst [c])) -> (ORconst [c] x)
|
||||
(XOR x (MOVWconst [c])) -> (XORconst [c] x)
|
||||
(NOR x (MOVWconst [c])) -> (NORconst [c] x)
|
||||
(ADD x (MOVWconst [c])) => (ADDconst [c] x)
|
||||
(SUB x (MOVWconst [c])) => (SUBconst [c] x)
|
||||
(AND x (MOVWconst [c])) => (ANDconst [c] x)
|
||||
(OR x (MOVWconst [c])) => (ORconst [c] x)
|
||||
(XOR x (MOVWconst [c])) => (XORconst [c] x)
|
||||
(NOR x (MOVWconst [c])) => (NORconst [c] x)
|
||||
|
||||
(SLL _ (MOVWconst [c])) && uint32(c)>=32 -> (MOVWconst [0])
|
||||
(SRL _ (MOVWconst [c])) && uint32(c)>=32 -> (MOVWconst [0])
|
||||
(SRA x (MOVWconst [c])) && uint32(c)>=32 -> (SRAconst x [31])
|
||||
(SLL x (MOVWconst [c])) -> (SLLconst x [c])
|
||||
(SRL x (MOVWconst [c])) -> (SRLconst x [c])
|
||||
(SRA x (MOVWconst [c])) -> (SRAconst x [c])
|
||||
(SRA x (MOVWconst [c])) && c >= 32 => (SRAconst x [31])
|
||||
(SLL x (MOVWconst [c])) => (SLLconst x [c])
|
||||
(SRL x (MOVWconst [c])) => (SRLconst x [c])
|
||||
(SRA x (MOVWconst [c])) => (SRAconst x [c])
|
||||
|
||||
(SGT (MOVWconst [c]) x) -> (SGTconst [c] x)
|
||||
(SGTU (MOVWconst [c]) x) -> (SGTUconst [c] x)
|
||||
(SGT x (MOVWconst [0])) -> (SGTzero x)
|
||||
(SGTU x (MOVWconst [0])) -> (SGTUzero x)
|
||||
(SGT (MOVWconst [c]) x) => (SGTconst [c] x)
|
||||
(SGTU (MOVWconst [c]) x) => (SGTUconst [c] x)
|
||||
(SGT x (MOVWconst [0])) => (SGTzero x)
|
||||
(SGTU x (MOVWconst [0])) => (SGTUzero x)
|
||||
|
||||
// mul with constant
|
||||
(Select1 (MULTU (MOVWconst [0]) _ )) -> (MOVWconst [0])
|
||||
(Select0 (MULTU (MOVWconst [0]) _ )) -> (MOVWconst [0])
|
||||
(Select1 (MULTU (MOVWconst [1]) x )) -> x
|
||||
(Select0 (MULTU (MOVWconst [1]) _ )) -> (MOVWconst [0])
|
||||
(Select1 (MULTU (MOVWconst [-1]) x )) -> (NEG <x.Type> x)
|
||||
(Select0 (MULTU (MOVWconst [-1]) x )) -> (CMOVZ (ADDconst <x.Type> [-1] x) (MOVWconst [0]) x)
|
||||
(Select1 (MULTU (MOVWconst [c]) x )) && isPowerOfTwo(int64(uint32(c))) -> (SLLconst [log2(int64(uint32(c)))] x)
|
||||
(Select0 (MULTU (MOVWconst [c]) x )) && isPowerOfTwo(int64(uint32(c))) -> (SRLconst [32-log2(int64(uint32(c)))] x)
|
||||
(Select1 (MULTU (MOVWconst [0]) _ )) => (MOVWconst [0])
|
||||
(Select0 (MULTU (MOVWconst [0]) _ )) => (MOVWconst [0])
|
||||
(Select1 (MULTU (MOVWconst [1]) x )) => x
|
||||
(Select0 (MULTU (MOVWconst [1]) _ )) => (MOVWconst [0])
|
||||
(Select1 (MULTU (MOVWconst [-1]) x )) => (NEG <x.Type> x)
|
||||
(Select0 (MULTU (MOVWconst [-1]) x )) => (CMOVZ (ADDconst <x.Type> [-1] x) (MOVWconst [0]) x)
|
||||
(Select1 (MULTU (MOVWconst [c]) x )) && isPowerOfTwo(int64(uint32(c))) => (SLLconst [int32(log2uint32(int64(c)))] x)
|
||||
(Select0 (MULTU (MOVWconst [c]) x )) && isPowerOfTwo(int64(uint32(c))) => (SRLconst [int32(32-log2uint32(int64(c)))] x)
|
||||
|
||||
(MUL (MOVWconst [0]) _ ) -> (MOVWconst [0])
|
||||
(MUL (MOVWconst [1]) x ) -> x
|
||||
(MUL (MOVWconst [-1]) x ) -> (NEG x)
|
||||
(MUL (MOVWconst [c]) x ) && isPowerOfTwo(int64(uint32(c))) -> (SLLconst [log2(int64(uint32(c)))] x)
|
||||
(MUL (MOVWconst [0]) _ ) => (MOVWconst [0])
|
||||
(MUL (MOVWconst [1]) x ) => x
|
||||
(MUL (MOVWconst [-1]) x ) => (NEG x)
|
||||
(MUL (MOVWconst [c]) x ) && isPowerOfTwo(int64(uint32(c))) => (SLLconst [int32(log2uint32(int64(c)))] x)
|
||||
|
||||
// generic simplifications
|
||||
(ADD x (NEG y)) -> (SUB x y)
|
||||
(SUB x x) -> (MOVWconst [0])
|
||||
(SUB (MOVWconst [0]) x) -> (NEG x)
|
||||
(AND x x) -> x
|
||||
(OR x x) -> x
|
||||
(XOR x x) -> (MOVWconst [0])
|
||||
(ADD x (NEG y)) => (SUB x y)
|
||||
(SUB x x) => (MOVWconst [0])
|
||||
(SUB (MOVWconst [0]) x) => (NEG x)
|
||||
(AND x x) => x
|
||||
(OR x x) => x
|
||||
(XOR x x) => (MOVWconst [0])
|
||||
|
||||
// miscellaneous patterns generated by dec64
|
||||
(AND (SGTUconst [1] x) (SGTUconst [1] y)) -> (SGTUconst [1] (OR <x.Type> x y))
|
||||
(OR (SGTUzero x) (SGTUzero y)) -> (SGTUzero (OR <x.Type> x y))
|
||||
(AND (SGTUconst [1] x) (SGTUconst [1] y)) => (SGTUconst [1] (OR <x.Type> x y))
|
||||
(OR (SGTUzero x) (SGTUzero y)) => (SGTUzero (OR <x.Type> x y))
|
||||
|
||||
// remove redundant *const ops
|
||||
(ADDconst [0] x) -> x
|
||||
(SUBconst [0] x) -> x
|
||||
(ANDconst [0] _) -> (MOVWconst [0])
|
||||
(ANDconst [-1] x) -> x
|
||||
(ORconst [0] x) -> x
|
||||
(ORconst [-1] _) -> (MOVWconst [-1])
|
||||
(XORconst [0] x) -> x
|
||||
(XORconst [-1] x) -> (NORconst [0] x)
|
||||
(ADDconst [0] x) => x
|
||||
(SUBconst [0] x) => x
|
||||
(ANDconst [0] _) => (MOVWconst [0])
|
||||
(ANDconst [-1] x) => x
|
||||
(ORconst [0] x) => x
|
||||
(ORconst [-1] _) => (MOVWconst [-1])
|
||||
(XORconst [0] x) => x
|
||||
(XORconst [-1] x) => (NORconst [0] x)
|
||||
|
||||
// generic constant folding
|
||||
(ADDconst [c] (MOVWconst [d])) -> (MOVWconst [int64(int32(c+d))])
|
||||
(ADDconst [c] (ADDconst [d] x)) -> (ADDconst [int64(int32(c+d))] x)
|
||||
(ADDconst [c] (SUBconst [d] x)) -> (ADDconst [int64(int32(c-d))] x)
|
||||
(SUBconst [c] (MOVWconst [d])) -> (MOVWconst [int64(int32(d-c))])
|
||||
(SUBconst [c] (SUBconst [d] x)) -> (ADDconst [int64(int32(-c-d))] x)
|
||||
(SUBconst [c] (ADDconst [d] x)) -> (ADDconst [int64(int32(-c+d))] x)
|
||||
(SLLconst [c] (MOVWconst [d])) -> (MOVWconst [int64(int32(uint32(d)<<uint32(c)))])
|
||||
(SRLconst [c] (MOVWconst [d])) -> (MOVWconst [int64(uint32(d)>>uint32(c))])
|
||||
(SRAconst [c] (MOVWconst [d])) -> (MOVWconst [int64(int32(d)>>uint32(c))])
|
||||
(MUL (MOVWconst [c]) (MOVWconst [d])) -> (MOVWconst [int64(int32(c)*int32(d))])
|
||||
(Select1 (MULTU (MOVWconst [c]) (MOVWconst [d]))) -> (MOVWconst [int64(int32(uint32(c)*uint32(d)))])
|
||||
(Select0 (MULTU (MOVWconst [c]) (MOVWconst [d]))) -> (MOVWconst [(c*d)>>32])
|
||||
(Select1 (DIV (MOVWconst [c]) (MOVWconst [d]))) -> (MOVWconst [int64(int32(c)/int32(d))])
|
||||
(Select1 (DIVU (MOVWconst [c]) (MOVWconst [d]))) -> (MOVWconst [int64(int32(uint32(c)/uint32(d)))])
|
||||
(Select0 (DIV (MOVWconst [c]) (MOVWconst [d]))) -> (MOVWconst [int64(int32(c)%int32(d))])
|
||||
(Select0 (DIVU (MOVWconst [c]) (MOVWconst [d]))) -> (MOVWconst [int64(int32(uint32(c)%uint32(d)))])
|
||||
(ANDconst [c] (MOVWconst [d])) -> (MOVWconst [c&d])
|
||||
(ANDconst [c] (ANDconst [d] x)) -> (ANDconst [c&d] x)
|
||||
(ORconst [c] (MOVWconst [d])) -> (MOVWconst [c|d])
|
||||
(ORconst [c] (ORconst [d] x)) -> (ORconst [c|d] x)
|
||||
(XORconst [c] (MOVWconst [d])) -> (MOVWconst [c^d])
|
||||
(XORconst [c] (XORconst [d] x)) -> (XORconst [c^d] x)
|
||||
(NORconst [c] (MOVWconst [d])) -> (MOVWconst [^(c|d)])
|
||||
(NEG (MOVWconst [c])) -> (MOVWconst [int64(int32(-c))])
|
||||
(MOVBreg (MOVWconst [c])) -> (MOVWconst [int64(int8(c))])
|
||||
(MOVBUreg (MOVWconst [c])) -> (MOVWconst [int64(uint8(c))])
|
||||
(MOVHreg (MOVWconst [c])) -> (MOVWconst [int64(int16(c))])
|
||||
(MOVHUreg (MOVWconst [c])) -> (MOVWconst [int64(uint16(c))])
|
||||
(MOVWreg (MOVWconst [c])) -> (MOVWconst [c])
|
||||
(ADDconst [c] (MOVWconst [d])) => (MOVWconst [int32(c+d)])
|
||||
(ADDconst [c] (ADDconst [d] x)) => (ADDconst [c+d] x)
|
||||
(ADDconst [c] (SUBconst [d] x)) => (ADDconst [c-d] x)
|
||||
(SUBconst [c] (MOVWconst [d])) => (MOVWconst [d-c])
|
||||
(SUBconst [c] (SUBconst [d] x)) => (ADDconst [-c-d] x)
|
||||
(SUBconst [c] (ADDconst [d] x)) => (ADDconst [-c+d] x)
|
||||
(SLLconst [c] (MOVWconst [d])) => (MOVWconst [d<<uint32(c)])
|
||||
(SRLconst [c] (MOVWconst [d])) => (MOVWconst [int32(uint32(d)>>uint32(c))])
|
||||
(SRAconst [c] (MOVWconst [d])) => (MOVWconst [d>>uint32(c)])
|
||||
(MUL (MOVWconst [c]) (MOVWconst [d])) => (MOVWconst [c*d])
|
||||
(Select1 (MULTU (MOVWconst [c]) (MOVWconst [d]))) => (MOVWconst [int32(uint32(c)*uint32(d))])
|
||||
(Select0 (MULTU (MOVWconst [c]) (MOVWconst [d]))) => (MOVWconst [int32((int64(uint32(c))*int64(uint32(d)))>>32)])
|
||||
(Select1 (DIV (MOVWconst [c]) (MOVWconst [d]))) => (MOVWconst [c/d])
|
||||
(Select1 (DIVU (MOVWconst [c]) (MOVWconst [d]))) => (MOVWconst [int32(uint32(c)/uint32(d))])
|
||||
(Select0 (DIV (MOVWconst [c]) (MOVWconst [d]))) => (MOVWconst [c%d])
|
||||
(Select0 (DIVU (MOVWconst [c]) (MOVWconst [d]))) => (MOVWconst [int32(uint32(c)%uint32(d))])
|
||||
(ANDconst [c] (MOVWconst [d])) => (MOVWconst [c&d])
|
||||
(ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x)
|
||||
(ORconst [c] (MOVWconst [d])) => (MOVWconst [c|d])
|
||||
(ORconst [c] (ORconst [d] x)) => (ORconst [c|d] x)
|
||||
(XORconst [c] (MOVWconst [d])) => (MOVWconst [c^d])
|
||||
(XORconst [c] (XORconst [d] x)) => (XORconst [c^d] x)
|
||||
(NORconst [c] (MOVWconst [d])) => (MOVWconst [^(c|d)])
|
||||
(NEG (MOVWconst [c])) => (MOVWconst [-c])
|
||||
(MOVBreg (MOVWconst [c])) => (MOVWconst [int32(int8(c))])
|
||||
(MOVBUreg (MOVWconst [c])) => (MOVWconst [int32(uint8(c))])
|
||||
(MOVHreg (MOVWconst [c])) => (MOVWconst [int32(int16(c))])
|
||||
(MOVHUreg (MOVWconst [c])) => (MOVWconst [int32(uint16(c))])
|
||||
(MOVWreg (MOVWconst [c])) => (MOVWconst [c])
|
||||
|
||||
// constant comparisons
|
||||
(SGTconst [c] (MOVWconst [d])) && int32(c) > int32(d) -> (MOVWconst [1])
|
||||
(SGTconst [c] (MOVWconst [d])) && int32(c) <= int32(d) -> (MOVWconst [0])
|
||||
(SGTUconst [c] (MOVWconst [d])) && uint32(c)>uint32(d) -> (MOVWconst [1])
|
||||
(SGTUconst [c] (MOVWconst [d])) && uint32(c)<=uint32(d) -> (MOVWconst [0])
|
||||
(SGTzero (MOVWconst [d])) && int32(d) > 0 -> (MOVWconst [1])
|
||||
(SGTzero (MOVWconst [d])) && int32(d) <= 0 -> (MOVWconst [0])
|
||||
(SGTUzero (MOVWconst [d])) && uint32(d) != 0 -> (MOVWconst [1])
|
||||
(SGTUzero (MOVWconst [d])) && uint32(d) == 0 -> (MOVWconst [0])
|
||||
(SGTconst [c] (MOVWconst [d])) && c > d => (MOVWconst [1])
|
||||
(SGTconst [c] (MOVWconst [d])) && c <= d => (MOVWconst [0])
|
||||
(SGTUconst [c] (MOVWconst [d])) && uint32(c) > uint32(d) => (MOVWconst [1])
|
||||
(SGTUconst [c] (MOVWconst [d])) && uint32(c) <= uint32(d) => (MOVWconst [0])
|
||||
(SGTzero (MOVWconst [d])) && d > 0 => (MOVWconst [1])
|
||||
(SGTzero (MOVWconst [d])) && d <= 0 => (MOVWconst [0])
|
||||
(SGTUzero (MOVWconst [d])) && d != 0 => (MOVWconst [1])
|
||||
(SGTUzero (MOVWconst [d])) && d == 0 => (MOVWconst [0])
|
||||
|
||||
// other known comparisons
|
||||
(SGTconst [c] (MOVBreg _)) && 0x7f < int32(c) -> (MOVWconst [1])
|
||||
(SGTconst [c] (MOVBreg _)) && int32(c) <= -0x80 -> (MOVWconst [0])
|
||||
(SGTconst [c] (MOVBUreg _)) && 0xff < int32(c) -> (MOVWconst [1])
|
||||
(SGTconst [c] (MOVBUreg _)) && int32(c) < 0 -> (MOVWconst [0])
|
||||
(SGTUconst [c] (MOVBUreg _)) && 0xff < uint32(c) -> (MOVWconst [1])
|
||||
(SGTconst [c] (MOVHreg _)) && 0x7fff < int32(c) -> (MOVWconst [1])
|
||||
(SGTconst [c] (MOVHreg _)) && int32(c) <= -0x8000 -> (MOVWconst [0])
|
||||
(SGTconst [c] (MOVHUreg _)) && 0xffff < int32(c) -> (MOVWconst [1])
|
||||
(SGTconst [c] (MOVHUreg _)) && int32(c) < 0 -> (MOVWconst [0])
|
||||
(SGTUconst [c] (MOVHUreg _)) && 0xffff < uint32(c) -> (MOVWconst [1])
|
||||
(SGTconst [c] (ANDconst [m] _)) && 0 <= int32(m) && int32(m) < int32(c) -> (MOVWconst [1])
|
||||
(SGTUconst [c] (ANDconst [m] _)) && uint32(m) < uint32(c) -> (MOVWconst [1])
|
||||
(SGTconst [c] (SRLconst _ [d])) && 0 <= int32(c) && uint32(d) <= 31 && 0xffffffff>>uint32(d) < uint32(c) -> (MOVWconst [1])
|
||||
(SGTUconst [c] (SRLconst _ [d])) && uint32(d) <= 31 && 0xffffffff>>uint32(d) < uint32(c) -> (MOVWconst [1])
|
||||
(SGTconst [c] (MOVBreg _)) && 0x7f < c => (MOVWconst [1])
|
||||
(SGTconst [c] (MOVBreg _)) && c <= -0x80 => (MOVWconst [0])
|
||||
(SGTconst [c] (MOVBUreg _)) && 0xff < c => (MOVWconst [1])
|
||||
(SGTconst [c] (MOVBUreg _)) && c < 0 => (MOVWconst [0])
|
||||
(SGTUconst [c] (MOVBUreg _)) && 0xff < uint32(c) => (MOVWconst [1])
|
||||
(SGTconst [c] (MOVHreg _)) && 0x7fff < c => (MOVWconst [1])
|
||||
(SGTconst [c] (MOVHreg _)) && c <= -0x8000 => (MOVWconst [0])
|
||||
(SGTconst [c] (MOVHUreg _)) && 0xffff < c => (MOVWconst [1])
|
||||
(SGTconst [c] (MOVHUreg _)) && c < 0 => (MOVWconst [0])
|
||||
(SGTUconst [c] (MOVHUreg _)) && 0xffff < uint32(c) => (MOVWconst [1])
|
||||
(SGTconst [c] (ANDconst [m] _)) && 0 <= m && m < c => (MOVWconst [1])
|
||||
(SGTUconst [c] (ANDconst [m] _)) && uint32(m) < uint32(c) => (MOVWconst [1])
|
||||
(SGTconst [c] (SRLconst _ [d])) && 0 <= c && uint32(d) <= 31 && 0xffffffff>>uint32(d) < uint32(c) => (MOVWconst [1])
|
||||
(SGTUconst [c] (SRLconst _ [d])) && uint32(d) <= 31 && 0xffffffff>>uint32(d) < uint32(c) => (MOVWconst [1])
|
||||
|
||||
// absorb constants into branches
|
||||
(EQ (MOVWconst [0]) yes no) -> (First yes no)
|
||||
(EQ (MOVWconst [c]) yes no) && c != 0 -> (First no yes)
|
||||
(NE (MOVWconst [0]) yes no) -> (First no yes)
|
||||
(NE (MOVWconst [c]) yes no) && c != 0 -> (First yes no)
|
||||
(LTZ (MOVWconst [c]) yes no) && int32(c) < 0 -> (First yes no)
|
||||
(LTZ (MOVWconst [c]) yes no) && int32(c) >= 0 -> (First no yes)
|
||||
(LEZ (MOVWconst [c]) yes no) && int32(c) <= 0 -> (First yes no)
|
||||
(LEZ (MOVWconst [c]) yes no) && int32(c) > 0 -> (First no yes)
|
||||
(GTZ (MOVWconst [c]) yes no) && int32(c) > 0 -> (First yes no)
|
||||
(GTZ (MOVWconst [c]) yes no) && int32(c) <= 0 -> (First no yes)
|
||||
(GEZ (MOVWconst [c]) yes no) && int32(c) >= 0 -> (First yes no)
|
||||
(GEZ (MOVWconst [c]) yes no) && int32(c) < 0 -> (First no yes)
|
||||
(EQ (MOVWconst [0]) yes no) => (First yes no)
|
||||
(EQ (MOVWconst [c]) yes no) && c != 0 => (First no yes)
|
||||
(NE (MOVWconst [0]) yes no) => (First no yes)
|
||||
(NE (MOVWconst [c]) yes no) && c != 0 => (First yes no)
|
||||
(LTZ (MOVWconst [c]) yes no) && c < 0 => (First yes no)
|
||||
(LTZ (MOVWconst [c]) yes no) && c >= 0 => (First no yes)
|
||||
(LEZ (MOVWconst [c]) yes no) && c <= 0 => (First yes no)
|
||||
(LEZ (MOVWconst [c]) yes no) && c > 0 => (First no yes)
|
||||
(GTZ (MOVWconst [c]) yes no) && c > 0 => (First yes no)
|
||||
(GTZ (MOVWconst [c]) yes no) && c <= 0 => (First no yes)
|
||||
(GEZ (MOVWconst [c]) yes no) && c >= 0 => (First yes no)
|
||||
(GEZ (MOVWconst [c]) yes no) && c < 0 => (First no yes)
|
||||
|
||||
// conditional move
|
||||
(CMOVZ _ f (MOVWconst [0])) -> f
|
||||
(CMOVZ a _ (MOVWconst [c])) && c!=0 -> a
|
||||
(CMOVZzero _ (MOVWconst [0])) -> (MOVWconst [0])
|
||||
(CMOVZzero a (MOVWconst [c])) && c!=0 -> a
|
||||
(CMOVZ a (MOVWconst [0]) c) -> (CMOVZzero a c)
|
||||
(CMOVZ _ f (MOVWconst [0])) => f
|
||||
(CMOVZ a _ (MOVWconst [c])) && c!=0 => a
|
||||
(CMOVZzero _ (MOVWconst [0])) => (MOVWconst [0])
|
||||
(CMOVZzero a (MOVWconst [c])) && c!=0 => a
|
||||
(CMOVZ a (MOVWconst [0]) c) => (CMOVZzero a c)
|
||||
|
||||
// atomic
|
||||
(LoweredAtomicStore32 ptr (MOVWconst [0]) mem) -> (LoweredAtomicStorezero ptr mem)
|
||||
(LoweredAtomicAdd ptr (MOVWconst [c]) mem) && is16Bit(c) -> (LoweredAtomicAddconst [c] ptr mem)
|
||||
(LoweredAtomicStore32 ptr (MOVWconst [0]) mem) => (LoweredAtomicStorezero ptr mem)
|
||||
(LoweredAtomicAdd ptr (MOVWconst [c]) mem) && is16Bit(int64(c)) => (LoweredAtomicAddconst [c] ptr mem)
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue