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cmd/compile: enable address folding for global symbols of shared library 

Address folding is disabled in CL42172, the commit message of which
said that "In shared library, load/store of global is rewritten to
using GOT and temp register, which conflicts with the use of temp
register for assembling large offset.". Actually this doesn't happen
because the sequence of instructions when rewritten to use Got looks
like this:
  MOVD $sym, Rx becomes
  MOVD sym@GOT, Rx
If there is an offset off, there will be one more instruction:
  ADD $off, Rx, Rx

And MOVD sym, Rx becomes
  MOVD sym@GOT, REGTMP
  MOVx (REGTMP), Ry

If there is a small offset off, it becomes:
  MOVD sym@GOT, REGTMP
  MOVx (REGTMP)off, Ry

If off is very large, it becomes:
  MOVD sym@GOT, REGTMP
  MOVD $off, Rt
  ADD  Rt, REGTMP
  MOVx (REGTMP), Ry

We can see that the address can be calculated correctly, and testing
on darwin/arm64 confirms this.

Removing this restriction is beneficial to further optimize the sequence
of "ADRP+ADD+LD/ST" to "ADRP+LD/ST(offset), so this CL removes it.

Change-Id: I0e9f7bc1723e0a027f32cf0ae2c41cd6df49defe
Reviewed-on: https://go-review.googlesource.com/c/go/+/445535
Reviewed-by: Cherry Mui <cherryyz@google.com>
Run-TryBot: Eric Fang <eric.fang@arm.com>
Reviewed-by: Heschi Kreinick <heschi@google.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
This commit is contained in:
erifan01 2022-10-25 12:08:05 +08:00 committed by Eric Fang
parent 8a9e2d9d49
commit e09bbaec69
2 changed files with 132 additions and 209 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

132
src/cmd/compile/internal/ssa/_gen/ARM64.rules
View File

@ -837,35 +837,25 @@
(MOVDaddr [int32(off1)+off2] {sym} ptr) (MOVDaddr [int32(off1)+off2] {sym} ptr)
// fold address into load/store // fold address into load/store
(MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVBload [off1+int32(off2)] {sym} ptr mem) (MOVBload [off1+int32(off2)] {sym} ptr mem)
(MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) (MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVBUload [off1+int32(off2)] {sym} ptr mem) (MOVBUload [off1+int32(off2)] {sym} ptr mem)
(MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVHload [off1+int32(off2)] {sym} ptr mem) (MOVHload [off1+int32(off2)] {sym} ptr mem)
(MOVHUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) (MOVHUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVHUload [off1+int32(off2)] {sym} ptr mem) (MOVHUload [off1+int32(off2)] {sym} ptr mem)
(MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVWload [off1+int32(off2)] {sym} ptr mem) (MOVWload [off1+int32(off2)] {sym} ptr mem)
(MOVWUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) (MOVWUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVWUload [off1+int32(off2)] {sym} ptr mem) (MOVWUload [off1+int32(off2)] {sym} ptr mem)
(MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVDload [off1+int32(off2)] {sym} ptr mem) (MOVDload [off1+int32(off2)] {sym} ptr mem)
(LDP [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) (LDP [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(LDP [off1+int32(off2)] {sym} ptr mem) (LDP [off1+int32(off2)] {sym} ptr mem)
(FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(FMOVSload [off1+int32(off2)] {sym} ptr mem) (FMOVSload [off1+int32(off2)] {sym} ptr mem)
(FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(FMOVDload [off1+int32(off2)] {sym} ptr mem) (FMOVDload [off1+int32(off2)] {sym} ptr mem)
// register indexed load // register indexed load
@ -930,41 +920,29 @@
(FMOVDloadidx8 ptr (MOVDconst [c]) mem) && is32Bit(c<<3) => (FMOVDload ptr [int32(c)<<3] mem) (FMOVDloadidx8 ptr (MOVDconst [c]) mem) && is32Bit(c<<3) => (FMOVDload ptr [int32(c)<<3] mem)
(FMOVSloadidx4 ptr (MOVDconst [c]) mem) && is32Bit(c<<2) => (FMOVSload ptr [int32(c)<<2] mem) (FMOVSloadidx4 ptr (MOVDconst [c]) mem) && is32Bit(c<<2) => (FMOVSload ptr [int32(c)<<2] mem)
(MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVBstore [off1+int32(off2)] {sym} ptr val mem) (MOVBstore [off1+int32(off2)] {sym} ptr val mem)
(MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVHstore [off1+int32(off2)] {sym} ptr val mem) (MOVHstore [off1+int32(off2)] {sym} ptr val mem)
(MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVWstore [off1+int32(off2)] {sym} ptr val mem) (MOVWstore [off1+int32(off2)] {sym} ptr val mem)
(MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVDstore [off1+int32(off2)] {sym} ptr val mem) (MOVDstore [off1+int32(off2)] {sym} ptr val mem)
(STP [off1] {sym} (ADDconst [off2] ptr) val1 val2 mem) && is32Bit(int64(off1)+off2) (STP [off1] {sym} (ADDconst [off2] ptr) val1 val2 mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(STP [off1+int32(off2)] {sym} ptr val1 val2 mem) (STP [off1+int32(off2)] {sym} ptr val1 val2 mem)
(FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(FMOVSstore [off1+int32(off2)] {sym} ptr val mem) (FMOVSstore [off1+int32(off2)] {sym} ptr val mem)
(FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(FMOVDstore [off1+int32(off2)] {sym} ptr val mem) (FMOVDstore [off1+int32(off2)] {sym} ptr val mem)
(MOVBstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) (MOVBstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVBstorezero [off1+int32(off2)] {sym} ptr mem) (MOVBstorezero [off1+int32(off2)] {sym} ptr mem)
(MOVHstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) (MOVHstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVHstorezero [off1+int32(off2)] {sym} ptr mem) (MOVHstorezero [off1+int32(off2)] {sym} ptr mem)
(MOVWstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) (MOVWstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVWstorezero [off1+int32(off2)] {sym} ptr mem) (MOVWstorezero [off1+int32(off2)] {sym} ptr mem)
(MOVDstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) (MOVDstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVDstorezero [off1+int32(off2)] {sym} ptr mem) (MOVDstorezero [off1+int32(off2)] {sym} ptr mem)
(MOVQstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) (MOVQstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVQstorezero [off1+int32(off2)] {sym} ptr mem) (MOVQstorezero [off1+int32(off2)] {sym} ptr mem)
// register indexed store // register indexed store
@ -1013,93 +991,71 @@
(FMOVSstoreidx4 ptr (MOVDconst [c]) val mem) && is32Bit(c<<2) => (FMOVSstore [int32(c)<<2] ptr val mem) (FMOVSstoreidx4 ptr (MOVDconst [c]) val mem) && is32Bit(c<<2) => (FMOVSstore [int32(c)<<2] ptr val mem)
(MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
(MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) (MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
(MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
(MOVHUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) (MOVHUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
(MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
(MOVWUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) (MOVWUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
(MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
(LDP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) (LDP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(LDP [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (LDP [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
(FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
(FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
(MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
(MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
(MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
(MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
(STP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem) (STP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(STP [off1+off2] {mergeSym(sym1,sym2)} ptr val1 val2 mem) (STP [off1+off2] {mergeSym(sym1,sym2)} ptr val1 val2 mem)
(FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
(FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
(MOVBstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) (MOVBstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
(MOVHstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) (MOVHstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
(MOVWstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) (MOVWstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
(MOVDstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) (MOVDstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
(MOVQstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) (MOVQstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
(MOVQstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVQstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
// store zero // store zero

209
src/cmd/compile/internal/ssa/rewriteARM64.go
View File

@ -4517,8 +4517,6 @@ func rewriteValueARM64_OpARM64FMOVDgpfp(v *Value) bool {
func rewriteValueARM64_OpARM64FMOVDload(v *Value) bool { func rewriteValueARM64_OpARM64FMOVDload(v *Value) bool {
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block
config := b.Func.Config
// match: (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr val _)) // match: (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr val _))
// result: (FMOVDgpfp val) // result: (FMOVDgpfp val)
for { for {
@ -4537,7 +4535,7 @@ func rewriteValueARM64_OpARM64FMOVDload(v *Value) bool {
return true return true
} }
// match: (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) // match: (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (FMOVDload [off1+int32(off2)] {sym} ptr mem) // result: (FMOVDload [off1+int32(off2)] {sym} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -4548,7 +4546,7 @@ func rewriteValueARM64_OpARM64FMOVDload(v *Value) bool {
off2 := auxIntToInt64(v_0.AuxInt) off2 := auxIntToInt64(v_0.AuxInt)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64FMOVDload) v.reset(OpARM64FMOVDload)
@ -4596,7 +4594,7 @@ func rewriteValueARM64_OpARM64FMOVDload(v *Value) bool {
return true return true
} }
// match: (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // match: (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) // result: (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -4608,7 +4606,7 @@ func rewriteValueARM64_OpARM64FMOVDload(v *Value) bool {
sym2 := auxToSym(v_0.Aux) sym2 := auxToSym(v_0.Aux)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64FMOVDload) v.reset(OpARM64FMOVDload)
@ -4715,8 +4713,6 @@ func rewriteValueARM64_OpARM64FMOVDstore(v *Value) bool {
v_2 := v.Args[2] v_2 := v.Args[2]
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block
config := b.Func.Config
// match: (FMOVDstore [off] {sym} ptr (FMOVDgpfp val) mem) // match: (FMOVDstore [off] {sym} ptr (FMOVDgpfp val) mem)
// result: (MOVDstore [off] {sym} ptr val mem) // result: (MOVDstore [off] {sym} ptr val mem)
for { for {
@ -4735,7 +4731,7 @@ func rewriteValueARM64_OpARM64FMOVDstore(v *Value) bool {
return true return true
} }
// match: (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) // match: (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (FMOVDstore [off1+int32(off2)] {sym} ptr val mem) // result: (FMOVDstore [off1+int32(off2)] {sym} ptr val mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -4747,7 +4743,7 @@ func rewriteValueARM64_OpARM64FMOVDstore(v *Value) bool {
ptr := v_0.Args[0] ptr := v_0.Args[0]
val := v_1 val := v_1
mem := v_2 mem := v_2
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64FMOVDstore) v.reset(OpARM64FMOVDstore)
@ -4797,7 +4793,7 @@ func rewriteValueARM64_OpARM64FMOVDstore(v *Value) bool {
return true return true
} }
// match: (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // match: (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) // result: (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -4810,7 +4806,7 @@ func rewriteValueARM64_OpARM64FMOVDstore(v *Value) bool {
ptr := v_0.Args[0] ptr := v_0.Args[0]
val := v_1 val := v_1
mem := v_2 mem := v_2
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64FMOVDstore) v.reset(OpARM64FMOVDstore)
@ -4923,8 +4919,6 @@ func rewriteValueARM64_OpARM64FMOVDstoreidx8(v *Value) bool {
func rewriteValueARM64_OpARM64FMOVSload(v *Value) bool { func rewriteValueARM64_OpARM64FMOVSload(v *Value) bool {
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block
config := b.Func.Config
// match: (FMOVSload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _)) // match: (FMOVSload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _))
// result: (FMOVSgpfp val) // result: (FMOVSgpfp val)
for { for {
@ -4943,7 +4937,7 @@ func rewriteValueARM64_OpARM64FMOVSload(v *Value) bool {
return true return true
} }
// match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) // match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (FMOVSload [off1+int32(off2)] {sym} ptr mem) // result: (FMOVSload [off1+int32(off2)] {sym} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -4954,7 +4948,7 @@ func rewriteValueARM64_OpARM64FMOVSload(v *Value) bool {
off2 := auxIntToInt64(v_0.AuxInt) off2 := auxIntToInt64(v_0.AuxInt)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64FMOVSload) v.reset(OpARM64FMOVSload)
@ -5002,7 +4996,7 @@ func rewriteValueARM64_OpARM64FMOVSload(v *Value) bool {
return true return true
} }
// match: (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // match: (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) // result: (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -5014,7 +5008,7 @@ func rewriteValueARM64_OpARM64FMOVSload(v *Value) bool {
sym2 := auxToSym(v_0.Aux) sym2 := auxToSym(v_0.Aux)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64FMOVSload) v.reset(OpARM64FMOVSload)
@ -5121,8 +5115,6 @@ func rewriteValueARM64_OpARM64FMOVSstore(v *Value) bool {
v_2 := v.Args[2] v_2 := v.Args[2]
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block
config := b.Func.Config
// match: (FMOVSstore [off] {sym} ptr (FMOVSgpfp val) mem) // match: (FMOVSstore [off] {sym} ptr (FMOVSgpfp val) mem)
// result: (MOVWstore [off] {sym} ptr val mem) // result: (MOVWstore [off] {sym} ptr val mem)
for { for {
@ -5141,7 +5133,7 @@ func rewriteValueARM64_OpARM64FMOVSstore(v *Value) bool {
return true return true
} }
// match: (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) // match: (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (FMOVSstore [off1+int32(off2)] {sym} ptr val mem) // result: (FMOVSstore [off1+int32(off2)] {sym} ptr val mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -5153,7 +5145,7 @@ func rewriteValueARM64_OpARM64FMOVSstore(v *Value) bool {
ptr := v_0.Args[0] ptr := v_0.Args[0]
val := v_1 val := v_1
mem := v_2 mem := v_2
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64FMOVSstore) v.reset(OpARM64FMOVSstore)
@ -5203,7 +5195,7 @@ func rewriteValueARM64_OpARM64FMOVSstore(v *Value) bool {
return true return true
} }
// match: (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // match: (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) // result: (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -5216,7 +5208,7 @@ func rewriteValueARM64_OpARM64FMOVSstore(v *Value) bool {
ptr := v_0.Args[0] ptr := v_0.Args[0]
val := v_1 val := v_1
mem := v_2 mem := v_2
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64FMOVSstore) v.reset(OpARM64FMOVSstore)
@ -5895,10 +5887,8 @@ func rewriteValueARM64_OpARM64GreaterThanU(v *Value) bool {
func rewriteValueARM64_OpARM64LDP(v *Value) bool { func rewriteValueARM64_OpARM64LDP(v *Value) bool {
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block
config := b.Func.Config
// match: (LDP [off1] {sym} (ADDconst [off2] ptr) mem) // match: (LDP [off1] {sym} (ADDconst [off2] ptr) mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (LDP [off1+int32(off2)] {sym} ptr mem) // result: (LDP [off1+int32(off2)] {sym} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -5909,7 +5899,7 @@ func rewriteValueARM64_OpARM64LDP(v *Value) bool {
off2 := auxIntToInt64(v_0.AuxInt) off2 := auxIntToInt64(v_0.AuxInt)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64LDP) v.reset(OpARM64LDP)
@ -5919,7 +5909,7 @@ func rewriteValueARM64_OpARM64LDP(v *Value) bool {
return true return true
} }
// match: (LDP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // match: (LDP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (LDP [off1+off2] {mergeSym(sym1,sym2)} ptr mem) // result: (LDP [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -5931,7 +5921,7 @@ func rewriteValueARM64_OpARM64LDP(v *Value) bool {
sym2 := auxToSym(v_0.Aux) sym2 := auxToSym(v_0.Aux)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64LDP) v.reset(OpARM64LDP)
@ -7598,10 +7588,8 @@ func rewriteValueARM64_OpARM64MODW(v *Value) bool {
func rewriteValueARM64_OpARM64MOVBUload(v *Value) bool { func rewriteValueARM64_OpARM64MOVBUload(v *Value) bool {
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block
config := b.Func.Config
// match: (MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) // match: (MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (MOVBUload [off1+int32(off2)] {sym} ptr mem) // result: (MOVBUload [off1+int32(off2)] {sym} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -7612,7 +7600,7 @@ func rewriteValueARM64_OpARM64MOVBUload(v *Value) bool {
off2 := auxIntToInt64(v_0.AuxInt) off2 := auxIntToInt64(v_0.AuxInt)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64MOVBUload) v.reset(OpARM64MOVBUload)
@ -7641,7 +7629,7 @@ func rewriteValueARM64_OpARM64MOVBUload(v *Value) bool {
return true return true
} }
// match: (MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // match: (MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) // result: (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -7653,7 +7641,7 @@ func rewriteValueARM64_OpARM64MOVBUload(v *Value) bool {
sym2 := auxToSym(v_0.Aux) sym2 := auxToSym(v_0.Aux)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64MOVBUload) v.reset(OpARM64MOVBUload)
@ -8041,10 +8029,8 @@ func rewriteValueARM64_OpARM64MOVBUreg(v *Value) bool {
func rewriteValueARM64_OpARM64MOVBload(v *Value) bool { func rewriteValueARM64_OpARM64MOVBload(v *Value) bool {
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block
config := b.Func.Config
// match: (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) // match: (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (MOVBload [off1+int32(off2)] {sym} ptr mem) // result: (MOVBload [off1+int32(off2)] {sym} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -8055,7 +8041,7 @@ func rewriteValueARM64_OpARM64MOVBload(v *Value) bool {
off2 := auxIntToInt64(v_0.AuxInt) off2 := auxIntToInt64(v_0.AuxInt)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64MOVBload) v.reset(OpARM64MOVBload)
@ -8084,7 +8070,7 @@ func rewriteValueARM64_OpARM64MOVBload(v *Value) bool {
return true return true
} }
// match: (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // match: (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -8096,7 +8082,7 @@ func rewriteValueARM64_OpARM64MOVBload(v *Value) bool {
sym2 := auxToSym(v_0.Aux) sym2 := auxToSym(v_0.Aux)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64MOVBload) v.reset(OpARM64MOVBload)
@ -8274,9 +8260,8 @@ func rewriteValueARM64_OpARM64MOVBstore(v *Value) bool {
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block b := v.Block
config := b.Func.Config
// match: (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) // match: (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (MOVBstore [off1+int32(off2)] {sym} ptr val mem) // result: (MOVBstore [off1+int32(off2)] {sym} ptr val mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -8288,7 +8273,7 @@ func rewriteValueARM64_OpARM64MOVBstore(v *Value) bool {
ptr := v_0.Args[0] ptr := v_0.Args[0]
val := v_1 val := v_1
mem := v_2 mem := v_2
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64MOVBstore) v.reset(OpARM64MOVBstore)
@ -8318,7 +8303,7 @@ func rewriteValueARM64_OpARM64MOVBstore(v *Value) bool {
return true return true
} }
// match: (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // match: (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -8331,7 +8316,7 @@ func rewriteValueARM64_OpARM64MOVBstore(v *Value) bool {
ptr := v_0.Args[0] ptr := v_0.Args[0]
val := v_1 val := v_1
mem := v_2 mem := v_2
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64MOVBstore) v.reset(OpARM64MOVBstore)
@ -10126,10 +10111,8 @@ func rewriteValueARM64_OpARM64MOVBstoreidx(v *Value) bool {
func rewriteValueARM64_OpARM64MOVBstorezero(v *Value) bool { func rewriteValueARM64_OpARM64MOVBstorezero(v *Value) bool {
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block
config := b.Func.Config
// match: (MOVBstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // match: (MOVBstorezero [off1] {sym} (ADDconst [off2] ptr) mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (MOVBstorezero [off1+int32(off2)] {sym} ptr mem) // result: (MOVBstorezero [off1+int32(off2)] {sym} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -10140,7 +10123,7 @@ func rewriteValueARM64_OpARM64MOVBstorezero(v *Value) bool {
off2 := auxIntToInt64(v_0.AuxInt) off2 := auxIntToInt64(v_0.AuxInt)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64MOVBstorezero) v.reset(OpARM64MOVBstorezero)
@ -10150,7 +10133,7 @@ func rewriteValueARM64_OpARM64MOVBstorezero(v *Value) bool {
return true return true
} }
// match: (MOVBstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // match: (MOVBstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) // result: (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -10162,7 +10145,7 @@ func rewriteValueARM64_OpARM64MOVBstorezero(v *Value) bool {
sym2 := auxToSym(v_0.Aux) sym2 := auxToSym(v_0.Aux)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64MOVBstorezero) v.reset(OpARM64MOVBstorezero)
@ -10337,7 +10320,7 @@ func rewriteValueARM64_OpARM64MOVDload(v *Value) bool {
return true return true
} }
// match: (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) // match: (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (MOVDload [off1+int32(off2)] {sym} ptr mem) // result: (MOVDload [off1+int32(off2)] {sym} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -10348,7 +10331,7 @@ func rewriteValueARM64_OpARM64MOVDload(v *Value) bool {
off2 := auxIntToInt64(v_0.AuxInt) off2 := auxIntToInt64(v_0.AuxInt)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64MOVDload) v.reset(OpARM64MOVDload)
@ -10396,7 +10379,7 @@ func rewriteValueARM64_OpARM64MOVDload(v *Value) bool {
return true return true
} }
// match: (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // match: (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -10408,7 +10391,7 @@ func rewriteValueARM64_OpARM64MOVDload(v *Value) bool {
sym2 := auxToSym(v_0.Aux) sym2 := auxToSym(v_0.Aux)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64MOVDload) v.reset(OpARM64MOVDload)
@ -10626,8 +10609,6 @@ func rewriteValueARM64_OpARM64MOVDstore(v *Value) bool {
v_2 := v.Args[2] v_2 := v.Args[2]
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block
config := b.Func.Config
// match: (MOVDstore [off] {sym} ptr (FMOVDfpgp val) mem) // match: (MOVDstore [off] {sym} ptr (FMOVDfpgp val) mem)
// result: (FMOVDstore [off] {sym} ptr val mem) // result: (FMOVDstore [off] {sym} ptr val mem)
for { for {
@ -10646,7 +10627,7 @@ func rewriteValueARM64_OpARM64MOVDstore(v *Value) bool {
return true return true
} }
// match: (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) // match: (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (MOVDstore [off1+int32(off2)] {sym} ptr val mem) // result: (MOVDstore [off1+int32(off2)] {sym} ptr val mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -10658,7 +10639,7 @@ func rewriteValueARM64_OpARM64MOVDstore(v *Value) bool {
ptr := v_0.Args[0] ptr := v_0.Args[0]
val := v_1 val := v_1
mem := v_2 mem := v_2
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64MOVDstore) v.reset(OpARM64MOVDstore)
@ -10708,7 +10689,7 @@ func rewriteValueARM64_OpARM64MOVDstore(v *Value) bool {
return true return true
} }
// match: (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // match: (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -10721,7 +10702,7 @@ func rewriteValueARM64_OpARM64MOVDstore(v *Value) bool {
ptr := v_0.Args[0] ptr := v_0.Args[0]
val := v_1 val := v_1
mem := v_2 mem := v_2
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64MOVDstore) v.reset(OpARM64MOVDstore)
@ -10876,10 +10857,8 @@ func rewriteValueARM64_OpARM64MOVDstoreidx8(v *Value) bool {
func rewriteValueARM64_OpARM64MOVDstorezero(v *Value) bool { func rewriteValueARM64_OpARM64MOVDstorezero(v *Value) bool {
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block
config := b.Func.Config
// match: (MOVDstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // match: (MOVDstorezero [off1] {sym} (ADDconst [off2] ptr) mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (MOVDstorezero [off1+int32(off2)] {sym} ptr mem) // result: (MOVDstorezero [off1+int32(off2)] {sym} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -10890,7 +10869,7 @@ func rewriteValueARM64_OpARM64MOVDstorezero(v *Value) bool {
off2 := auxIntToInt64(v_0.AuxInt) off2 := auxIntToInt64(v_0.AuxInt)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64MOVDstorezero) v.reset(OpARM64MOVDstorezero)
@ -10900,7 +10879,7 @@ func rewriteValueARM64_OpARM64MOVDstorezero(v *Value) bool {
return true return true
} }
// match: (MOVDstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // match: (MOVDstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) // result: (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -10912,7 +10891,7 @@ func rewriteValueARM64_OpARM64MOVDstorezero(v *Value) bool {
sym2 := auxToSym(v_0.Aux) sym2 := auxToSym(v_0.Aux)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64MOVDstorezero) v.reset(OpARM64MOVDstorezero)
@ -11151,7 +11130,7 @@ func rewriteValueARM64_OpARM64MOVHUload(v *Value) bool {
b := v.Block b := v.Block
config := b.Func.Config config := b.Func.Config
// match: (MOVHUload [off1] {sym} (ADDconst [off2] ptr) mem) // match: (MOVHUload [off1] {sym} (ADDconst [off2] ptr) mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (MOVHUload [off1+int32(off2)] {sym} ptr mem) // result: (MOVHUload [off1+int32(off2)] {sym} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -11162,7 +11141,7 @@ func rewriteValueARM64_OpARM64MOVHUload(v *Value) bool {
off2 := auxIntToInt64(v_0.AuxInt) off2 := auxIntToInt64(v_0.AuxInt)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64MOVHUload) v.reset(OpARM64MOVHUload)
@ -11210,7 +11189,7 @@ func rewriteValueARM64_OpARM64MOVHUload(v *Value) bool {
return true return true
} }
// match: (MOVHUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // match: (MOVHUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) // result: (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -11222,7 +11201,7 @@ func rewriteValueARM64_OpARM64MOVHUload(v *Value) bool {
sym2 := auxToSym(v_0.Aux) sym2 := auxToSym(v_0.Aux)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64MOVHUload) v.reset(OpARM64MOVHUload)
@ -11587,10 +11566,8 @@ func rewriteValueARM64_OpARM64MOVHUreg(v *Value) bool {
func rewriteValueARM64_OpARM64MOVHload(v *Value) bool { func rewriteValueARM64_OpARM64MOVHload(v *Value) bool {
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block
config := b.Func.Config
// match: (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) // match: (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (MOVHload [off1+int32(off2)] {sym} ptr mem) // result: (MOVHload [off1+int32(off2)] {sym} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -11601,7 +11578,7 @@ func rewriteValueARM64_OpARM64MOVHload(v *Value) bool {
off2 := auxIntToInt64(v_0.AuxInt) off2 := auxIntToInt64(v_0.AuxInt)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64MOVHload) v.reset(OpARM64MOVHload)
@ -11649,7 +11626,7 @@ func rewriteValueARM64_OpARM64MOVHload(v *Value) bool {
return true return true
} }
// match: (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // match: (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -11661,7 +11638,7 @@ func rewriteValueARM64_OpARM64MOVHload(v *Value) bool {
sym2 := auxToSym(v_0.Aux) sym2 := auxToSym(v_0.Aux)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64MOVHload) v.reset(OpARM64MOVHload)
@ -12003,9 +11980,8 @@ func rewriteValueARM64_OpARM64MOVHstore(v *Value) bool {
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block b := v.Block
config := b.Func.Config
// match: (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) // match: (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (MOVHstore [off1+int32(off2)] {sym} ptr val mem) // result: (MOVHstore [off1+int32(off2)] {sym} ptr val mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -12017,7 +11993,7 @@ func rewriteValueARM64_OpARM64MOVHstore(v *Value) bool {
ptr := v_0.Args[0] ptr := v_0.Args[0]
val := v_1 val := v_1
mem := v_2 mem := v_2
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64MOVHstore) v.reset(OpARM64MOVHstore)
@ -12067,7 +12043,7 @@ func rewriteValueARM64_OpARM64MOVHstore(v *Value) bool {
return true return true
} }
// match: (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // match: (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -12080,7 +12056,7 @@ func rewriteValueARM64_OpARM64MOVHstore(v *Value) bool {
ptr := v_0.Args[0] ptr := v_0.Args[0]
val := v_1 val := v_1
mem := v_2 mem := v_2
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64MOVHstore) v.reset(OpARM64MOVHstore)
@ -12881,9 +12857,8 @@ func rewriteValueARM64_OpARM64MOVHstorezero(v *Value) bool {
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block b := v.Block
config := b.Func.Config
// match: (MOVHstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // match: (MOVHstorezero [off1] {sym} (ADDconst [off2] ptr) mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (MOVHstorezero [off1+int32(off2)] {sym} ptr mem) // result: (MOVHstorezero [off1+int32(off2)] {sym} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -12894,7 +12869,7 @@ func rewriteValueARM64_OpARM64MOVHstorezero(v *Value) bool {
off2 := auxIntToInt64(v_0.AuxInt) off2 := auxIntToInt64(v_0.AuxInt)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64MOVHstorezero) v.reset(OpARM64MOVHstorezero)
@ -12904,7 +12879,7 @@ func rewriteValueARM64_OpARM64MOVHstorezero(v *Value) bool {
return true return true
} }
// match: (MOVHstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // match: (MOVHstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) // result: (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -12916,7 +12891,7 @@ func rewriteValueARM64_OpARM64MOVHstorezero(v *Value) bool {
sym2 := auxToSym(v_0.Aux) sym2 := auxToSym(v_0.Aux)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64MOVHstorezero) v.reset(OpARM64MOVHstorezero)
@ -13202,10 +13177,8 @@ func rewriteValueARM64_OpARM64MOVHstorezeroidx2(v *Value) bool {
func rewriteValueARM64_OpARM64MOVQstorezero(v *Value) bool { func rewriteValueARM64_OpARM64MOVQstorezero(v *Value) bool {
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block
config := b.Func.Config
// match: (MOVQstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // match: (MOVQstorezero [off1] {sym} (ADDconst [off2] ptr) mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (MOVQstorezero [off1+int32(off2)] {sym} ptr mem) // result: (MOVQstorezero [off1+int32(off2)] {sym} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -13216,7 +13189,7 @@ func rewriteValueARM64_OpARM64MOVQstorezero(v *Value) bool {
off2 := auxIntToInt64(v_0.AuxInt) off2 := auxIntToInt64(v_0.AuxInt)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64MOVQstorezero) v.reset(OpARM64MOVQstorezero)
@ -13226,7 +13199,7 @@ func rewriteValueARM64_OpARM64MOVQstorezero(v *Value) bool {
return true return true
} }
// match: (MOVQstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // match: (MOVQstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (MOVQstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) // result: (MOVQstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -13238,7 +13211,7 @@ func rewriteValueARM64_OpARM64MOVQstorezero(v *Value) bool {
sym2 := auxToSym(v_0.Aux) sym2 := auxToSym(v_0.Aux)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64MOVQstorezero) v.reset(OpARM64MOVQstorezero)
@ -13272,7 +13245,7 @@ func rewriteValueARM64_OpARM64MOVWUload(v *Value) bool {
return true return true
} }
// match: (MOVWUload [off1] {sym} (ADDconst [off2] ptr) mem) // match: (MOVWUload [off1] {sym} (ADDconst [off2] ptr) mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (MOVWUload [off1+int32(off2)] {sym} ptr mem) // result: (MOVWUload [off1+int32(off2)] {sym} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -13283,7 +13256,7 @@ func rewriteValueARM64_OpARM64MOVWUload(v *Value) bool {
off2 := auxIntToInt64(v_0.AuxInt) off2 := auxIntToInt64(v_0.AuxInt)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64MOVWUload) v.reset(OpARM64MOVWUload)
@ -13331,7 +13304,7 @@ func rewriteValueARM64_OpARM64MOVWUload(v *Value) bool {
return true return true
} }
// match: (MOVWUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // match: (MOVWUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) // result: (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -13343,7 +13316,7 @@ func rewriteValueARM64_OpARM64MOVWUload(v *Value) bool {
sym2 := auxToSym(v_0.Aux) sym2 := auxToSym(v_0.Aux)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64MOVWUload) v.reset(OpARM64MOVWUload)
@ -13733,10 +13706,8 @@ func rewriteValueARM64_OpARM64MOVWUreg(v *Value) bool {
func rewriteValueARM64_OpARM64MOVWload(v *Value) bool { func rewriteValueARM64_OpARM64MOVWload(v *Value) bool {
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block
config := b.Func.Config
// match: (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) // match: (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (MOVWload [off1+int32(off2)] {sym} ptr mem) // result: (MOVWload [off1+int32(off2)] {sym} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -13747,7 +13718,7 @@ func rewriteValueARM64_OpARM64MOVWload(v *Value) bool {
off2 := auxIntToInt64(v_0.AuxInt) off2 := auxIntToInt64(v_0.AuxInt)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64MOVWload) v.reset(OpARM64MOVWload)
@ -13795,7 +13766,7 @@ func rewriteValueARM64_OpARM64MOVWload(v *Value) bool {
return true return true
} }
// match: (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // match: (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -13807,7 +13778,7 @@ func rewriteValueARM64_OpARM64MOVWload(v *Value) bool {
sym2 := auxToSym(v_0.Aux) sym2 := auxToSym(v_0.Aux)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64MOVWload) v.reset(OpARM64MOVWload)
@ -14207,7 +14178,6 @@ func rewriteValueARM64_OpARM64MOVWstore(v *Value) bool {
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block b := v.Block
config := b.Func.Config
// match: (MOVWstore [off] {sym} ptr (FMOVSfpgp val) mem) // match: (MOVWstore [off] {sym} ptr (FMOVSfpgp val) mem)
// result: (FMOVSstore [off] {sym} ptr val mem) // result: (FMOVSstore [off] {sym} ptr val mem)
for { for {
@ -14226,7 +14196,7 @@ func rewriteValueARM64_OpARM64MOVWstore(v *Value) bool {
return true return true
} }
// match: (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) // match: (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (MOVWstore [off1+int32(off2)] {sym} ptr val mem) // result: (MOVWstore [off1+int32(off2)] {sym} ptr val mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -14238,7 +14208,7 @@ func rewriteValueARM64_OpARM64MOVWstore(v *Value) bool {
ptr := v_0.Args[0] ptr := v_0.Args[0]
val := v_1 val := v_1
mem := v_2 mem := v_2
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64MOVWstore) v.reset(OpARM64MOVWstore)
@ -14288,7 +14258,7 @@ func rewriteValueARM64_OpARM64MOVWstore(v *Value) bool {
return true return true
} }
// match: (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // match: (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -14301,7 +14271,7 @@ func rewriteValueARM64_OpARM64MOVWstore(v *Value) bool {
ptr := v_0.Args[0] ptr := v_0.Args[0]
val := v_1 val := v_1
mem := v_2 mem := v_2
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64MOVWstore) v.reset(OpARM64MOVWstore)
@ -14772,9 +14742,8 @@ func rewriteValueARM64_OpARM64MOVWstorezero(v *Value) bool {
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block b := v.Block
config := b.Func.Config
// match: (MOVWstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // match: (MOVWstorezero [off1] {sym} (ADDconst [off2] ptr) mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (MOVWstorezero [off1+int32(off2)] {sym} ptr mem) // result: (MOVWstorezero [off1+int32(off2)] {sym} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -14785,7 +14754,7 @@ func rewriteValueARM64_OpARM64MOVWstorezero(v *Value) bool {
off2 := auxIntToInt64(v_0.AuxInt) off2 := auxIntToInt64(v_0.AuxInt)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64MOVWstorezero) v.reset(OpARM64MOVWstorezero)
@ -14795,7 +14764,7 @@ func rewriteValueARM64_OpARM64MOVWstorezero(v *Value) bool {
return true return true
} }
// match: (MOVWstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // match: (MOVWstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) // result: (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -14807,7 +14776,7 @@ func rewriteValueARM64_OpARM64MOVWstorezero(v *Value) bool {
sym2 := auxToSym(v_0.Aux) sym2 := auxToSym(v_0.Aux)
ptr := v_0.Args[0] ptr := v_0.Args[0]
mem := v_1 mem := v_1
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64MOVWstorezero) v.reset(OpARM64MOVWstorezero)
@ -21669,10 +21638,8 @@ func rewriteValueARM64_OpARM64STP(v *Value) bool {
v_2 := v.Args[2] v_2 := v.Args[2]
v_1 := v.Args[1] v_1 := v.Args[1]
v_0 := v.Args[0] v_0 := v.Args[0]
b := v.Block
config := b.Func.Config
// match: (STP [off1] {sym} (ADDconst [off2] ptr) val1 val2 mem) // match: (STP [off1] {sym} (ADDconst [off2] ptr) val1 val2 mem)
// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: is32Bit(int64(off1)+off2)
// result: (STP [off1+int32(off2)] {sym} ptr val1 val2 mem) // result: (STP [off1+int32(off2)] {sym} ptr val1 val2 mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -21685,7 +21652,7 @@ func rewriteValueARM64_OpARM64STP(v *Value) bool {
val1 := v_1 val1 := v_1
val2 := v_2 val2 := v_2
mem := v_3 mem := v_3
if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(is32Bit(int64(off1) + off2)) {
break break
} }
v.reset(OpARM64STP) v.reset(OpARM64STP)
@ -21695,7 +21662,7 @@ func rewriteValueARM64_OpARM64STP(v *Value) bool {
return true return true
} }
// match: (STP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem) // match: (STP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem)
// cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
// result: (STP [off1+off2] {mergeSym(sym1,sym2)} ptr val1 val2 mem) // result: (STP [off1+off2] {mergeSym(sym1,sym2)} ptr val1 val2 mem)
for { for {
off1 := auxIntToInt32(v.AuxInt) off1 := auxIntToInt32(v.AuxInt)
@ -21709,7 +21676,7 @@ func rewriteValueARM64_OpARM64STP(v *Value) bool {
val1 := v_1 val1 := v_1
val2 := v_2 val2 := v_2
mem := v_3 mem := v_3
if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2))) {
break break
} }
v.reset(OpARM64STP) v.reset(OpARM64STP)