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cmd/compile: clean up ADDconst on PPC64 

ADDconst op is no longer used for addresses, as we lower Addr to
MOVDaddr. There is no rule that produces ADDconst with a non-nil
sym. So we can remove the sym aux field in ADDconst and limit its
use for adding constant (not offset to symbol).

Passes "toolstash -cmp" on std cmd for GOARCH=ppc64 and ppc64le.

Change-Id: Icee35cdb34d8d121ad7035076dfd07595c7ff809
Reviewed-on: https://go-review.googlesource.com/69450
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com>
This commit is contained in:
Cherry Zhang 2017-10-10 10:26:35 -04:00
parent 7557423994
commit d5a2925b7d
4 changed files with 13 additions and 22 deletions
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11
src/cmd/compile/internal/ppc64/ssa.go
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@ -593,15 +593,8 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
ssa.OpPPC64SRADconst, ssa.OpPPC64SRAWconst, ssa.OpPPC64SRDconst, ssa.OpPPC64SRWconst, ssa.OpPPC64SLDconst, ssa.OpPPC64SLWconst: ssa.OpPPC64SRADconst, ssa.OpPPC64SRAWconst, ssa.OpPPC64SRDconst, ssa.OpPPC64SRWconst, ssa.OpPPC64SLDconst, ssa.OpPPC64SLWconst:
p := s.Prog(v.Op.Asm()) p := s.Prog(v.Op.Asm())
p.Reg = v.Args[0].Reg() p.Reg = v.Args[0].Reg()
p.From.Type = obj.TYPE_CONST
if v.Aux != nil { p.From.Offset = v.AuxInt
p.From.Type = obj.TYPE_CONST
p.From.Offset = gc.AuxOffset(v)
} else {
p.From.Type = obj.TYPE_CONST
p.From.Offset = v.AuxInt
}
p.To.Type = obj.TYPE_REG p.To.Type = obj.TYPE_REG
p.To.Reg = v.Reg() p.To.Reg = v.Reg()

1
src/cmd/compile/internal/ssa/gen/PPC64.rules
View File

@ -287,7 +287,6 @@
// (MaskIfNotCarry CarrySet) -> -1 // (MaskIfNotCarry CarrySet) -> -1
(Addr {sym} base) -> (MOVDaddr {sym} base) (Addr {sym} base) -> (MOVDaddr {sym} base)
// (Addr {sym} base) -> (ADDconst {sym} base)
(OffPtr [off] ptr) -> (ADD (MOVDconst <typ.Int64> [off]) ptr) (OffPtr [off] ptr) -> (ADD (MOVDconst <typ.Int64> [off]) ptr)
(Ctz64 x) -> (POPCNTD (ANDN <typ.Int64> (ADDconst <typ.Int64> [-1] x) x)) (Ctz64 x) -> (POPCNTD (ANDN <typ.Int64> (ADDconst <typ.Int64> [-1] x) x))

14
src/cmd/compile/internal/ssa/gen/PPC64Ops.go
View File

@ -155,13 +155,13 @@ func init() {
callerSave = regMask(gp | fp | gr) callerSave = regMask(gp | fp | gr)
) )
ops := []opData{ ops := []opData{
{name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true}, // arg0 + arg1 {name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true}, // arg0 + arg1
{name: "ADDconst", argLength: 1, reg: gp11, asm: "ADD", aux: "SymOff", symEffect: "Addr"}, // arg0 + auxInt + aux.(*gc.Sym) {name: "ADDconst", argLength: 1, reg: gp11, asm: "ADD", aux: "Int64"}, // arg0 + auxInt
{name: "FADD", argLength: 2, reg: fp21, asm: "FADD", commutative: true}, // arg0+arg1 {name: "FADD", argLength: 2, reg: fp21, asm: "FADD", commutative: true}, // arg0+arg1
{name: "FADDS", argLength: 2, reg: fp21, asm: "FADDS", commutative: true}, // arg0+arg1 {name: "FADDS", argLength: 2, reg: fp21, asm: "FADDS", commutative: true}, // arg0+arg1
{name: "SUB", argLength: 2, reg: gp21, asm: "SUB"}, // arg0-arg1 {name: "SUB", argLength: 2, reg: gp21, asm: "SUB"}, // arg0-arg1
{name: "FSUB", argLength: 2, reg: fp21, asm: "FSUB"}, // arg0-arg1 {name: "FSUB", argLength: 2, reg: fp21, asm: "FSUB"}, // arg0-arg1
{name: "FSUBS", argLength: 2, reg: fp21, asm: "FSUBS"}, // arg0-arg1 {name: "FSUBS", argLength: 2, reg: fp21, asm: "FSUBS"}, // arg0-arg1
{name: "MULLD", argLength: 2, reg: gp21, asm: "MULLD", typ: "Int64", commutative: true}, // arg0*arg1 (signed 64-bit) {name: "MULLD", argLength: 2, reg: gp21, asm: "MULLD", typ: "Int64", commutative: true}, // arg0*arg1 (signed 64-bit)
{name: "MULLW", argLength: 2, reg: gp21, asm: "MULLW", typ: "Int32", commutative: true}, // arg0*arg1 (signed 32-bit) {name: "MULLW", argLength: 2, reg: gp21, asm: "MULLW", typ: "Int32", commutative: true}, // arg0*arg1 (signed 32-bit)

9
src/cmd/compile/internal/ssa/opGen.go
View File

@ -16713,11 +16713,10 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "ADDconst", name: "ADDconst",
auxType: auxSymOff, auxType: auxInt64,
argLen: 1, argLen: 1,
symEffect: SymAddr, asm: ppc64.AADD,
asm: ppc64.AADD,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29