mirror of https://github.com/golang/go.git
[dev.simd] cmd/compile: add simdGen prog writer
This CL is a synergy between simdgen refactor CL 681195. Change-Id: I365becf515a261bd22c46824613c2dce309cac45 Reviewed-on: https://go-review.googlesource.com/c/go/+/681036 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Junyang Shao
parent
9b9af3d638
commit
c81cb05e3e
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@ -1517,24 +1517,70 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
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}
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}
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func simdGenUnary(s *ssagen.State, v *ssa.Value) {
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// Example instruction: VRSQRTPS X1, X1
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func simdFp11(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = simdReg(v.Args[0])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = simdReg(v)
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return p
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}
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func simdGenBinary(s *ssagen.State, v *ssa.Value) {
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// Example instruction: VPSUBD X1, X2, X3
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func simdFp21(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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// Vector registers operands follows a right-to-left order.
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// e.g. VPSUBD X1, X2, X3 means X3 = X2 - X1.
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p.From.Reg = simdReg(v.Args[1])
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p.AddRestSourceReg(simdReg(v.Args[0]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = simdReg(v)
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return p
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}
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// Example instruction: VPCMPEQW Z26, Z30, K4
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func simdFp2k1(s *ssagen.State, v *ssa.Value) *obj.Prog {
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// simdReg handles mask and vector registers altogether
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return simdFp21(s, v)
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}
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// Example instruction: VPMINUQ X21, X3, K3, X31
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func simdFp2k1fp1(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = simdReg(v.Args[1])
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p.AddRestSourceReg(simdReg(v.Args[0]))
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// These "simd*" series of functions assumes:
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// Any "K" register that serves as the write-mask
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// or "predicate" for "predicated AVX512 instructions"
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// sits right at the end of the operand list.
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// TODO: verify this assumption.
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p.AddRestSourceReg(simdReg(v.Args[2]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = simdReg(v)
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return p
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}
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// Example instruction: VPCMPEQW Z26, Z30, K1, K4
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func simdFp2k1k1(s *ssagen.State, v *ssa.Value) *obj.Prog {
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return simdFp2k1fp1(s, v)
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}
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// Example instruction: VPOPCNTB X14, K4, X16
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func simdFp1k1fp1(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = simdReg(v.Args[0])
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p.AddRestSourceReg(simdReg(v.Args[1]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = simdReg(v)
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return p
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}
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func simdGenUnaryImmUint8(s *ssagen.State, v *ssa.Value) {
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// Example instruction: VROUNDPD $7, X2, X2
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func simdFp11Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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imm := v.AuxInt
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if imm < 0 || imm > 255 {
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@ -1545,9 +1591,11 @@ func simdGenUnaryImmUint8(s *ssagen.State, v *ssa.Value) {
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p.AddRestSourceReg(simdReg(v.Args[0]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = simdReg(v)
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return p
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}
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func simdGenBinaryImmUint8(s *ssagen.State, v *ssa.Value) {
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// Example instruction: VREDUCEPD $126, X1, K3, X31
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func simdFp1k1fp1Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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imm := v.AuxInt
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if imm < 0 || imm > 255 {
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@ -1559,6 +1607,93 @@ func simdGenBinaryImmUint8(s *ssagen.State, v *ssa.Value) {
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p.AddRestSourceReg(simdReg(v.Args[1]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = simdReg(v)
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return p
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}
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// Example instruction: VCMPPS $7, X2, X9, X2
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func simdFp21Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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imm := v.AuxInt
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if imm < 0 || imm > 255 {
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v.Fatalf("Invalid source selection immediate")
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}
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p.From.Offset = imm
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p.From.Type = obj.TYPE_CONST
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p.AddRestSourceReg(simdReg(v.Args[1]))
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p.AddRestSourceReg(simdReg(v.Args[0]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = simdReg(v)
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return p
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}
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// Example instruction: VPCMPD $1, Z1, Z2, K1
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func simdFp2k1Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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return simdFp21Imm8(s, v)
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}
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// Example instruction: VPCMPD $1, Z1, Z2, K2, K1
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func simdFp2k1k1Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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imm := v.AuxInt
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if imm < 0 || imm > 255 {
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v.Fatalf("Invalid source selection immediate")
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}
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p.From.Offset = imm
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p.From.Type = obj.TYPE_CONST
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p.AddRestSourceReg(simdReg(v.Args[1]))
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p.AddRestSourceReg(simdReg(v.Args[0]))
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p.AddRestSourceReg(simdReg(v.Args[2]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = simdReg(v)
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return p
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}
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// Example instruction: VFMADD213PD Z2, Z1, Z0
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func simdFp31ResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = simdReg(v.Args[2])
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p.AddRestSourceReg(simdReg(v.Args[1]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = simdReg(v)
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return p
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}
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// Example instruction: VFMADD213PD Z2, Z1, K1, Z0
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func simdFp3k1fp1ResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = simdReg(v.Args[2])
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p.AddRestSourceReg(simdReg(v.Args[1]))
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p.AddRestSourceReg(simdReg(v.Args[3]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = simdReg(v)
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return p
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}
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// Currently unused
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func simdFp31(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = simdReg(v.Args[2])
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p.AddRestSourceReg(simdReg(v.Args[1]))
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p.AddRestSourceReg(simdReg(v.Args[0]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = simdReg(v)
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return p
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}
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// Currently unused
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func simdFp3k1fp1(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = simdReg(v.Args[2])
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p.AddRestSourceReg(simdReg(v.Args[1]))
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p.AddRestSourceReg(simdReg(v.Args[0]))
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p.AddRestSourceReg(simdReg(v.Args[3]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = simdReg(v)
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return p
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}
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var blockJump = [...]struct {
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@ -182,14 +182,14 @@ func init() {
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fpstore = regInfo{inputs: []regMask{gpspsb, fp, 0}}
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fpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, fp, 0}}
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fp1m1 = regInfo{inputs: fponly, outputs: maskonly}
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m1fp1 = regInfo{inputs: maskonly, outputs: fponly}
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fp2m1 = regInfo{inputs: []regMask{fp, fp}, outputs: maskonly}
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fp1m1fp1 = regInfo{inputs: []regMask{fp, mask}, outputs: fponly}
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fp2m1fp1 = regInfo{inputs: []regMask{fp, fp, mask}, outputs: fponly}
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fp2m1m1 = regInfo{inputs: []regMask{fp, fp, mask}, outputs: maskonly}
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fp1k1 = regInfo{inputs: fponly, outputs: maskonly}
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k1fp1 = regInfo{inputs: maskonly, outputs: fponly}
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fp2k1 = regInfo{inputs: []regMask{fp, fp}, outputs: maskonly}
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fp1k1fp1 = regInfo{inputs: []regMask{fp, mask}, outputs: fponly}
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fp2k1fp1 = regInfo{inputs: []regMask{fp, fp, mask}, outputs: fponly}
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fp2k1k1 = regInfo{inputs: []regMask{fp, fp, mask}, outputs: maskonly}
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fp3fp1 = regInfo{inputs: []regMask{fp, fp, fp}, outputs: fponly}
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fp3m1fp1 = regInfo{inputs: []regMask{fp, fp, fp, mask}, outputs: fponly}
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fp3k1fp1 = regInfo{inputs: []regMask{fp, fp, fp, mask}, outputs: fponly}
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prefreg = regInfo{inputs: []regMask{gpspsbg}}
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)
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@ -1233,37 +1233,37 @@ func init() {
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{name: "VMOVDQUload512", argLength: 2, reg: fpload, asm: "VMOVDQU64", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0+auxint+aux, arg1 = mem
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{name: "VMOVDQUstore512", argLength: 3, reg: fpstore, asm: "VMOVDQU64", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg1, arg2 = mem
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{name: "VPMOVMToVec8x16", argLength: 1, reg: m1fp1, asm: "VPMOVM2B"},
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{name: "VPMOVMToVec8x32", argLength: 1, reg: m1fp1, asm: "VPMOVM2B"},
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{name: "VPMOVMToVec8x64", argLength: 1, reg: m1fp1, asm: "VPMOVM2B"},
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{name: "VPMOVMToVec8x16", argLength: 1, reg: k1fp1, asm: "VPMOVM2B"},
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{name: "VPMOVMToVec8x32", argLength: 1, reg: k1fp1, asm: "VPMOVM2B"},
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{name: "VPMOVMToVec8x64", argLength: 1, reg: k1fp1, asm: "VPMOVM2B"},
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{name: "VPMOVMToVec16x8", argLength: 1, reg: m1fp1, asm: "VPMOVM2W"},
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{name: "VPMOVMToVec16x16", argLength: 1, reg: m1fp1, asm: "VPMOVM2W"},
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{name: "VPMOVMToVec16x32", argLength: 1, reg: m1fp1, asm: "VPMOVM2W"},
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{name: "VPMOVMToVec16x8", argLength: 1, reg: k1fp1, asm: "VPMOVM2W"},
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{name: "VPMOVMToVec16x16", argLength: 1, reg: k1fp1, asm: "VPMOVM2W"},
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{name: "VPMOVMToVec16x32", argLength: 1, reg: k1fp1, asm: "VPMOVM2W"},
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{name: "VPMOVMToVec32x4", argLength: 1, reg: m1fp1, asm: "VPMOVM2D"},
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{name: "VPMOVMToVec32x8", argLength: 1, reg: m1fp1, asm: "VPMOVM2D"},
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{name: "VPMOVMToVec32x16", argLength: 1, reg: m1fp1, asm: "VPMOVM2D"},
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{name: "VPMOVMToVec32x4", argLength: 1, reg: k1fp1, asm: "VPMOVM2D"},
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{name: "VPMOVMToVec32x8", argLength: 1, reg: k1fp1, asm: "VPMOVM2D"},
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{name: "VPMOVMToVec32x16", argLength: 1, reg: k1fp1, asm: "VPMOVM2D"},
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{name: "VPMOVMToVec64x2", argLength: 1, reg: m1fp1, asm: "VPMOVM2Q"},
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{name: "VPMOVMToVec64x4", argLength: 1, reg: m1fp1, asm: "VPMOVM2Q"},
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{name: "VPMOVMToVec64x8", argLength: 1, reg: m1fp1, asm: "VPMOVM2Q"},
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{name: "VPMOVMToVec64x2", argLength: 1, reg: k1fp1, asm: "VPMOVM2Q"},
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{name: "VPMOVMToVec64x4", argLength: 1, reg: k1fp1, asm: "VPMOVM2Q"},
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{name: "VPMOVMToVec64x8", argLength: 1, reg: k1fp1, asm: "VPMOVM2Q"},
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{name: "VPMOVVec8x16ToM", argLength: 1, reg: fp1m1, asm: "VPMOVB2M"},
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{name: "VPMOVVec8x32ToM", argLength: 1, reg: fp1m1, asm: "VPMOVB2M"},
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{name: "VPMOVVec8x64ToM", argLength: 1, reg: fp1m1, asm: "VPMOVB2M"},
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{name: "VPMOVVec8x16ToM", argLength: 1, reg: fp1k1, asm: "VPMOVB2M"},
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{name: "VPMOVVec8x32ToM", argLength: 1, reg: fp1k1, asm: "VPMOVB2M"},
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{name: "VPMOVVec8x64ToM", argLength: 1, reg: fp1k1, asm: "VPMOVB2M"},
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{name: "VPMOVVec16x8ToM", argLength: 1, reg: fp1m1, asm: "VPMOVW2M"},
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{name: "VPMOVVec16x16ToM", argLength: 1, reg: fp1m1, asm: "VPMOVW2M"},
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{name: "VPMOVVec16x32ToM", argLength: 1, reg: fp1m1, asm: "VPMOVW2M"},
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{name: "VPMOVVec16x8ToM", argLength: 1, reg: fp1k1, asm: "VPMOVW2M"},
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{name: "VPMOVVec16x16ToM", argLength: 1, reg: fp1k1, asm: "VPMOVW2M"},
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{name: "VPMOVVec16x32ToM", argLength: 1, reg: fp1k1, asm: "VPMOVW2M"},
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{name: "VPMOVVec32x4ToM", argLength: 1, reg: fp1m1, asm: "VPMOVD2M"},
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{name: "VPMOVVec32x8ToM", argLength: 1, reg: fp1m1, asm: "VPMOVD2M"},
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{name: "VPMOVVec32x16ToM", argLength: 1, reg: fp1m1, asm: "VPMOVD2M"},
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{name: "VPMOVVec32x4ToM", argLength: 1, reg: fp1k1, asm: "VPMOVD2M"},
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{name: "VPMOVVec32x8ToM", argLength: 1, reg: fp1k1, asm: "VPMOVD2M"},
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{name: "VPMOVVec32x16ToM", argLength: 1, reg: fp1k1, asm: "VPMOVD2M"},
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{name: "VPMOVVec64x2ToM", argLength: 1, reg: fp1m1, asm: "VPMOVQ2M"},
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{name: "VPMOVVec64x4ToM", argLength: 1, reg: fp1m1, asm: "VPMOVQ2M"},
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{name: "VPMOVVec64x8ToM", argLength: 1, reg: fp1m1, asm: "VPMOVQ2M"},
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{name: "VPMOVVec64x2ToM", argLength: 1, reg: fp1k1, asm: "VPMOVQ2M"},
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{name: "VPMOVVec64x4ToM", argLength: 1, reg: fp1k1, asm: "VPMOVQ2M"},
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{name: "VPMOVVec64x8ToM", argLength: 1, reg: fp1k1, asm: "VPMOVQ2M"},
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{name: "Zero128", argLength: 0, reg: fp01, asm: "VPXOR"},
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{name: "Zero256", argLength: 0, reg: fp01, asm: "VPXOR"},
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@ -1300,7 +1300,7 @@ func init() {
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pkg: "cmd/internal/obj/x86",
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genfile: "../../amd64/ssa.go",
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genSIMDfile: "../../amd64/simdssa.go",
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ops: append(AMD64ops, simdAMD64Ops(fp11, fp21, fp2m1, fp1m1fp1, fp2m1fp1, fp2m1m1, fp3fp1, fp3m1fp1)...), // AMD64ops,
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ops: append(AMD64ops, simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp3fp1, fp3k1fp1)...), // AMD64ops,
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blocks: AMD64blocks,
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regnames: regNamesAMD64,
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ParamIntRegNames: "AX BX CX DI SI R8 R9 R10 R11",
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