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cmd/internal/obj/arm: remove illegal form of the SWI instruction 

SWI only support "SWI $imm", but currently "SWI (Reg)" is also
accepted. This patch fixes it.

And more instruction tests are added to cmd/asm/internal/asm/testdata/arm.s

fixes #20375

Change-Id: Id437d853924a403e41da9b6cbddd20d994b624ff
Reviewed-on: https://go-review.googlesource.com/43552
Run-TryBot: Brad Fitzpatrick <bradfitz@golang.org>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
This commit is contained in:
Ben Shi 2017-05-16 11:36:54 +00:00 committed by Cherry Zhang
parent 0927b4728d
commit c7cae34b19
2 changed files with 38 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
src/cmd/asm/internal/asm/testdata/arm.s vendored
View File

@ -103,9 +103,9 @@ TEXT foo(SB), DUPOK|NOSPLIT, $0
// { // {
// outcode($1, $2, &nullgen, 0, &$4); // outcode($1, $2, &nullgen, 0, &$4);
// } // }
SWI.S $2 SWI $2
SWI.S (R1) SWI $3
// SWI.S foo(SB) - TODO: classifying foo(SB) as C_TLS_LE // SWI foo(SB) - TODO: classifying foo(SB) as C_TLS_LE
// //
// CMP // CMP
@ -956,8 +956,20 @@ jmp_label_3:
MMULA R1, R2, R3, R4 // 123154e7 MMULA R1, R2, R3, R4 // 123154e7
MMULS R1, R2, R3, R4 // d23154e7 MMULS R1, R2, R3, R4 // d23154e7
MULABB R1, R2, R3, R4 // 823104e1 MULABB R1, R2, R3, R4 // 823104e1
MULAL R1, R2, (R4, R3) // 9231e4e0
MULAL.S R1, R2, (R4, R3) // 9231f4e0
MULALU R1, R2, (R4, R3) // 9231a4e0
MULALU.S R1, R2, (R4, R3) // 9231b4e0
// MUL // MUL
MUL R2, R3, R4 // 930204e0
MUL.S R2, R3, R4 // 930214e0
MULU R5, R6, R7 // 960507e0
MULU.S R5, R6, R7 // 960517e0
MULLU R1, R2, (R4, R3) // 923184e0
MULLU.S R1, R2, (R4, R3) // 923194e0
MULL R1, R2, (R4, R3) // 9231c4e0
MULL.S R1, R2, (R4, R3) // 9231d4e0
MMUL R1, R2, R3 // 12f153e7 MMUL R1, R2, R3 // 12f153e7
MULBB R1, R2, R3 // 82f163e1 MULBB R1, R2, R3 // 82f163e1
MULWB R1, R2, R3 // a20123e1 MULWB R1, R2, R3 // a20123e1
@ -976,6 +988,21 @@ jmp_label_3:
DIVHW R0, R1 // 11f011e7 DIVHW R0, R1 // 11f011e7
DIVUHW R0, R1 // 11f031e7 DIVUHW R0, R1 // 11f031e7
// misc
CLZ R1, R2 // 112f6fe1
WORD $0 // 00000000
WORD $4294967295 // ffffffff
WORD $2863311530 // aaaaaaaa
WORD $1431655765 // 55555555
PLD 4080(R6) // f0ffd6f5
PLD -4080(R9) // f0ff59f5
RFE // 0080fde8
SWPW R3, (R7), R9 // SWPW (R7), R3, R9 // 939007e1
SWPBU R4, (R2), R8 // SWPBU (R2), R4, R8 // 948042e1
SWI $0 // 000000ef
SWI $65535 // ffff00ef
SWI // 000000ef
// //
// END // END
// //

1
src/cmd/internal/obj/arm/asm5.go
View File

@ -127,7 +127,6 @@ var optab = []Optab{
{ASLL, C_REG, C_NONE, C_REG, 9, 4, 0, 0, 0}, {ASLL, C_REG, C_NONE, C_REG, 9, 4, 0, 0, 0},
{ASLL, C_REG, C_REG, C_REG, 9, 4, 0, 0, 0}, {ASLL, C_REG, C_REG, C_REG, 9, 4, 0, 0, 0},
{ASWI, C_NONE, C_NONE, C_NONE, 10, 4, 0, 0, 0}, {ASWI, C_NONE, C_NONE, C_NONE, 10, 4, 0, 0, 0},
{ASWI, C_NONE, C_NONE, C_LOREG, 10, 4, 0, 0, 0},
{ASWI, C_NONE, C_NONE, C_LCON, 10, 4, 0, 0, 0}, {ASWI, C_NONE, C_NONE, C_LCON, 10, 4, 0, 0, 0},
{AWORD, C_NONE, C_NONE, C_LCON, 11, 4, 0, 0, 0}, {AWORD, C_NONE, C_NONE, C_LCON, 11, 4, 0, 0, 0},
{AWORD, C_NONE, C_NONE, C_LCONADDR, 11, 4, 0, 0, 0}, {AWORD, C_NONE, C_NONE, C_LCONADDR, 11, 4, 0, 0, 0},