mirror of https://github.com/golang/go.git
cmd,cmd/vendor: pick up updates for golang.org/x/arch/ppc64
Bring in updates to golang.org/x/arch/ppc64 to add new instructions from CLs 260617, 230957, 249158. Used the directions found in README.vendor: cd $GOROOT/src/cmd go get -d golang.org/x/arch@latest go mod tidy go mod vendor Change-Id: Ie8ceb9c804928b72b37fff5b63981c174fb86989 Reviewed-on: https://go-review.googlesource.com/c/go/+/264079 Trust: Lynn Boger <laboger@linux.vnet.ibm.com> Run-TryBot: Lynn Boger <laboger@linux.vnet.ibm.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
This commit is contained in:
Lynn Boger
parent
ed2010e676
commit
b4c8b67adc
|
|
@ -5,7 +5,7 @@ go 1.16
|
|||
require (
|
||||
github.com/google/pprof v0.0.0-20200708004538-1a94d8640e99
|
||||
github.com/ianlancetaylor/demangle v0.0.0-20200414190113-039b1ae3a340 // indirect
|
||||
golang.org/x/arch v0.0.0-20200826200359-b19915210f00
|
||||
golang.org/x/arch v0.0.0-20201008161808-52c3e6f60cff
|
||||
golang.org/x/crypto v0.0.0-20200820211705-5c72a883971a
|
||||
golang.org/x/mod v0.3.1-0.20200828183125-ce943fd02449
|
||||
golang.org/x/sys v0.0.0-20200923182605-d9f96fdee20d // indirect
|
||||
|
|
|
|||
|
|
@ -7,8 +7,8 @@ github.com/ianlancetaylor/demangle v0.0.0-20181102032728-5e5cf60278f6/go.mod h1:
|
|||
github.com/ianlancetaylor/demangle v0.0.0-20200414190113-039b1ae3a340 h1:S1+yTUaFPXuDZnPDbO+TrDFIjPzQraYH8/CwSlu9Fac=
|
||||
github.com/ianlancetaylor/demangle v0.0.0-20200414190113-039b1ae3a340/go.mod h1:aSSvb/t6k1mPoxDqO4vJh6VOCGPwU4O0C2/Eqndh1Sc=
|
||||
github.com/yuin/goldmark v1.2.1/go.mod h1:3hX8gzYuyVAZsxl0MRgGTJEmQBFcNTphYh9decYSb74=
|
||||
golang.org/x/arch v0.0.0-20200826200359-b19915210f00 h1:cfd5G6xu8iZTFmjBYVemyBmE/sTf0A3vpE3BmoOuLCI=
|
||||
golang.org/x/arch v0.0.0-20200826200359-b19915210f00/go.mod h1:flIaEI6LNU6xOCD5PaJvn9wGP0agmIOqjrtsKGRguv4=
|
||||
golang.org/x/arch v0.0.0-20201008161808-52c3e6f60cff h1:XmKBi9R6duxOB3lfc72wyrwiOY7X2Jl1wuI+RFOyMDE=
|
||||
golang.org/x/arch v0.0.0-20201008161808-52c3e6f60cff/go.mod h1:flIaEI6LNU6xOCD5PaJvn9wGP0agmIOqjrtsKGRguv4=
|
||||
golang.org/x/crypto v0.0.0-20190308221718-c2843e01d9a2/go.mod h1:djNgcEr1/C05ACkg1iLfiJU5Ep61QUkGW8qpdssI0+w=
|
||||
golang.org/x/crypto v0.0.0-20191011191535-87dc89f01550/go.mod h1:yigFU9vqHzYiE8UmvKecakEJjdnWj3jj499lnFckfCI=
|
||||
golang.org/x/crypto v0.0.0-20200622213623-75b288015ac9/go.mod h1:LzIPMQfyMNhhGPhUkYOs5KpL4U8rLKemX1yGLhDgUto=
|
||||
|
|
|
|||
|
|
@ -112,7 +112,7 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) strin
|
|||
case STDCXCC, STWCXCC, STHCXCC, STBCXCC:
|
||||
return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"
|
||||
|
||||
case STXVX, STXVD2X, STXVW4X, STXSDX, STVX, STVXL, STVEBX, STVEHX, STVEWX, STXSIWX, STFDX, STFDUX, STFDPX, STFSX, STFSUX:
|
||||
case STXVX, STXVD2X, STXVW4X, STXVH8X, STXVB16X, STXSDX, STVX, STVXL, STVEBX, STVEHX, STVEWX, STXSIWX, STFDX, STFDUX, STFDPX, STFSX, STFSUX:
|
||||
return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"
|
||||
|
||||
case STXV:
|
||||
|
|
@ -127,7 +127,7 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) strin
|
|||
}
|
||||
return op + " (" + args[2] + ")(" + args[1] + ")," + args[0]
|
||||
|
||||
case LXVX, LXVD2X, LXVW4X, LVX, LVXL, LVSR, LVSL, LVEBX, LVEHX, LVEWX, LXSDX, LXSIWAX:
|
||||
case LXVX, LXVD2X, LXVW4X, LXVH8X, LXVB16X, LVX, LVXL, LVSR, LVSL, LVEBX, LVEHX, LVEWX, LXSDX, LXSIWAX:
|
||||
return op + " (" + args[2] + ")(" + args[1] + ")," + args[0]
|
||||
|
||||
case LXV:
|
||||
|
|
@ -332,6 +332,7 @@ var plan9OpMap = map[Op]string{
|
|||
DIVDUO: "DIVDUV",
|
||||
DIVDUOCC: "DIVDUVCC",
|
||||
ADDI: "ADD",
|
||||
MULLI: "MULLD",
|
||||
SRADI: "SRAD",
|
||||
SUBF: "SUB",
|
||||
STBCXCC: "STBCCC",
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
// DO NOT EDIT
|
||||
// generated by: ppc64map -fmt=decoder ../pp64.csv
|
||||
// generated by: ppc64map -fmt=decoder pp64.csv
|
||||
|
||||
package ppc64asm
|
||||
|
||||
|
|
@ -727,6 +727,8 @@ const (
|
|||
LXVD2X
|
||||
LXVDSX
|
||||
LXVW4X
|
||||
LXVH8X
|
||||
LXVB16X
|
||||
LXV
|
||||
LXVL
|
||||
LXVLL
|
||||
|
|
@ -736,6 +738,8 @@ const (
|
|||
STXSSPX
|
||||
STXVD2X
|
||||
STXVW4X
|
||||
STXVH8X
|
||||
STXVB16X
|
||||
STXV
|
||||
STXVL
|
||||
STXVLL
|
||||
|
|
@ -883,6 +887,9 @@ const (
|
|||
XXSEL
|
||||
XXSLDWI
|
||||
XXSPLTW
|
||||
XXBRD
|
||||
XXBRW
|
||||
XXBRH
|
||||
BRINC
|
||||
EVABS
|
||||
EVADDIW
|
||||
|
|
@ -2097,6 +2104,8 @@ var opstr = [...]string{
|
|||
LXVD2X: "lxvd2x",
|
||||
LXVDSX: "lxvdsx",
|
||||
LXVW4X: "lxvw4x",
|
||||
LXVH8X: "lxvh8x",
|
||||
LXVB16X: "lxvb16x",
|
||||
LXV: "lxv",
|
||||
LXVL: "lxvl",
|
||||
LXVLL: "lxvll",
|
||||
|
|
@ -2106,6 +2115,8 @@ var opstr = [...]string{
|
|||
STXSSPX: "stxsspx",
|
||||
STXVD2X: "stxvd2x",
|
||||
STXVW4X: "stxvw4x",
|
||||
STXVH8X: "stxvh8x",
|
||||
STXVB16X: "stxvb16x",
|
||||
STXV: "stxv",
|
||||
STXVL: "stxvl",
|
||||
STXVLL: "stxvll",
|
||||
|
|
@ -2253,6 +2264,9 @@ var opstr = [...]string{
|
|||
XXSEL: "xxsel",
|
||||
XXSLDWI: "xxsldwi",
|
||||
XXSPLTW: "xxspltw",
|
||||
XXBRD: "xxbrd",
|
||||
XXBRW: "xxbrw",
|
||||
XXBRH: "xxbrh",
|
||||
BRINC: "brinc",
|
||||
EVABS: "evabs",
|
||||
EVADDIW: "evaddiw",
|
||||
|
|
@ -4264,13 +4278,17 @@ var instFormats = [...]instFormat{
|
|||
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
|
||||
{LXVW4X, 0xfc0007fe, 0x7c000618, 0x0, // Load VSX Vector Word*4 Indexed XX1-form (lxvw4x XT,RA,RB)
|
||||
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
|
||||
{LXVH8X, 0xfc0007fe, 0x7c000658, 0x0, // Load VSX Vector Halfword*8 Indexed XX1-form (lxvh8x XT,RA,RB)
|
||||
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
|
||||
{LXVB16X, 0xfc0007fe, 0x7c0006d8, 0x0, // Load VSX Vector Byte*16 Indexed XX1-form (lxvb16x XT,RA,RB)
|
||||
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
|
||||
{LXV, 0xfc000007, 0xf4000001, 0x0, // Load VSX Vector DQ-form (lxv XT,DQ(RA))
|
||||
[5]*argField{ap_VecSReg_28_28_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
|
||||
{LXVL, 0xfc0007fe, 0x7c00021a, 0x0, // Load VSX Vector with Length X-form (lxvl XT,RA,RB)
|
||||
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
|
||||
{LXVLL, 0xfc0007fe, 0x7c00025a, 0x0, // Load VSX Vector Left-justified with Length X-form (lxvll XT,RA,RB)
|
||||
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
|
||||
{LXVX, 0xfc0007fe, 0x7c000218, 0x0, // Load VSX Vector Indexed X-form (lxvx XT,RA,RB)
|
||||
{LXVX, 0xfc0007be, 0x7c000218, 0x40, // Load VSX Vector Indexed X-form (lxvx XT,RA,RB)
|
||||
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
|
||||
{STXSDX, 0xfc0007fe, 0x7c000598, 0x0, // Store VSX Scalar Doubleword Indexed XX1-form (stxsdx XS,RA,RB)
|
||||
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
|
||||
|
|
@ -4282,6 +4300,10 @@ var instFormats = [...]instFormat{
|
|||
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
|
||||
{STXVW4X, 0xfc0007fe, 0x7c000718, 0x0, // Store VSX Vector Word*4 Indexed XX1-form (stxvw4x XS,RA,RB)
|
||||
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
|
||||
{STXVH8X, 0xfc0007fe, 0x7c000758, 0x0, // Store VSX Vector Halfword*4 Indexed XX1-form (stxvh8x XS,RA,RB)
|
||||
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
|
||||
{STXVB16X, 0xfc0007fe, 0x7c0007d8, 0x0, // Store VSX Vector Byte*16 Indexed XX1-form (stxvb16x XS,RA,RB)
|
||||
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
|
||||
{STXV, 0xfc000007, 0xf4000005, 0x0, // Store VSX Vector DQ-form (stxv XS,DQ(RA))
|
||||
[5]*argField{ap_VecSReg_28_28_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
|
||||
{STXVL, 0xfc0007fe, 0x7c00031a, 0x0, // Store VSX Vector with Length X-form (stxvl XS,RA,RB)
|
||||
|
|
@ -4576,6 +4598,12 @@ var instFormats = [...]instFormat{
|
|||
[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}},
|
||||
{XXSPLTW, 0xfc0007fc, 0xf0000290, 0x1c0000, // VSX Splat Word XX2-form (xxspltw XT,XB,UIM)
|
||||
[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_14_15}},
|
||||
{XXBRD, 0xfc1f07fc, 0xf017076c, 0x0, // VSX Vector Byte-Reverse Doubleword XX2-form (xxbrd XT,XB)
|
||||
[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
|
||||
{XXBRW, 0xfc1f07fc, 0xf00f076c, 0x0, // VSX Vector Byte-Reverse Word XX2-form (xxbrw XT,XB)
|
||||
[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
|
||||
{XXBRH, 0xfc1f07fc, 0xf007076c, 0x0, // VSX Vector Byte-Reverse Halfword XX2-form (xxbrh XT,XB)
|
||||
[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
|
||||
{BRINC, 0xfc0007ff, 0x1000020f, 0x0, // Bit Reversed Increment EVX-form (brinc RT,RA,RB)
|
||||
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
|
||||
{EVABS, 0xfc0007ff, 0x10000208, 0xf800, // Vector Absolute Value EVX-form (evabs RT,RA)
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ github.com/google/pprof/third_party/svgpan
|
|||
# github.com/ianlancetaylor/demangle v0.0.0-20200414190113-039b1ae3a340
|
||||
## explicit
|
||||
github.com/ianlancetaylor/demangle
|
||||
# golang.org/x/arch v0.0.0-20200826200359-b19915210f00
|
||||
# golang.org/x/arch v0.0.0-20201008161808-52c3e6f60cff
|
||||
## explicit
|
||||
golang.org/x/arch/arm/armasm
|
||||
golang.org/x/arch/arm64/arm64asm
|
||||
|
|
|
|||
Loading…
Reference in New Issue