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[release-branch.go1.8] cmd/compile: add zero-extension before right shift when lowering Lrot on ARM 

Fixes #19270.

Change-Id: Ie7538ff8465138a8bc02572e84cf5d00de7bbdd1
Reviewed-on: https://go-review.googlesource.com/37718
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Cherry Zhang 2017-03-03 12:22:55 -05:00
parent 6a712dfac1
commit b43fabfb30
3 changed files with 21 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/cmd/compile/internal/gc/testdata/arith.go vendored
View File

@ -488,6 +488,17 @@ func testLrot() {
wantA, wantB, wantC, wantD, ", got", a, b, c, d)
failed = true
}
// Also test inputs with the top bit set, and make sure
// sub-word right shift has high bits cleared first.
// See issue #19270.
wantA, wantB, wantC, wantD = uint8(0xdf), uint16(0xdfff),
uint32(0xdfffffff), uint64(0xdfffffffffffffff)
a, b, c, d = lrot1_ssa(0xfe, 0xfffe, 0xfffffffe, 0xfffffffffffffffe)
if a != wantA || b != wantB || c != wantC || d != wantD {
println("lrot1_ssa(0xfe, 0xfffe, 0xfffffffe, 0xfffffffffffffffe)=",
wantA, wantB, wantC, wantD, ", got", a, b, c, d)
failed = true
}
x := lrot2_ssa(0xb0000001, 32)
wantX := uint32(0xb0000001)
if x != wantX {

4
src/cmd/compile/internal/ssa/gen/ARM.rules
View File

@ -178,8 +178,8 @@
(Rsh8x64 x (Const64 [c])) && uint64(c) >= 8 -> (SRAconst (SLLconst <config.fe.TypeUInt32()> x [24]) [31])
(Lrot32 x [c]) -> (SRRconst x [32-c&31])
(Lrot16 <t> x [c]) -> (OR (SLLconst <t> x [c&15]) (SRLconst <t> x [16-c&15]))
(Lrot8 <t> x [c]) -> (OR (SLLconst <t> x [c&7]) (SRLconst <t> x [8-c&7]))
(Lrot16 <t> x [c]) -> (OR (SLLconst <t> x [c&15]) (SRLconst <t> (ZeroExt16to32 x) [16-c&15]))
(Lrot8 <t> x [c]) -> (OR (SLLconst <t> x [c&7]) (SRLconst <t> (ZeroExt8to32 x) [8-c&7]))
// constants
(Const8 [val]) -> (MOVWconst [val])

12
src/cmd/compile/internal/ssa/rewriteARM.go
View File

@ -14517,7 +14517,7 @@ func rewriteValueARM_OpLrot16(v *Value, config *Config) bool {
_ = b
// match: (Lrot16 <t> x [c])
// cond:
// result: (OR (SLLconst <t> x [c&15]) (SRLconst <t> x [16-c&15]))
// result: (OR (SLLconst <t> x [c&15]) (SRLconst <t> (ZeroExt16to32 x) [16-c&15]))
for {
t := v.Type
c := v.AuxInt
@ -14529,7 +14529,9 @@ func rewriteValueARM_OpLrot16(v *Value, config *Config) bool {
v.AddArg(v0)
v1 := b.NewValue0(v.Line, OpARMSRLconst, t)
v1.AuxInt = 16 - c&15
v1.AddArg(x)
v2 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
v2.AddArg(x)
v1.AddArg(v2)
v.AddArg(v1)
return true
}
@ -14554,7 +14556,7 @@ func rewriteValueARM_OpLrot8(v *Value, config *Config) bool {
_ = b
// match: (Lrot8 <t> x [c])
// cond:
// result: (OR (SLLconst <t> x [c&7]) (SRLconst <t> x [8-c&7]))
// result: (OR (SLLconst <t> x [c&7]) (SRLconst <t> (ZeroExt8to32 x) [8-c&7]))
for {
t := v.Type
c := v.AuxInt
@ -14566,7 +14568,9 @@ func rewriteValueARM_OpLrot8(v *Value, config *Config) bool {
v.AddArg(v0)
v1 := b.NewValue0(v.Line, OpARMSRLconst, t)
v1.AuxInt = 8 - c&7
v1.AddArg(x)
v2 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
v2.AddArg(x)
v1.AddArg(v2)
v.AddArg(v1)
return true
}