mirror of https://github.com/golang/go.git
[dev.ssa] cmd/internal/ssa: reorganize opcode tables
Separate out opcode tables into separate ranges for each architecture. Put architecture-specific opcodes into separate files. Comment each opcode in a consistent format. Change-Id: Iddf03c062bc8a88ad2bcebbf6528088c01a75779 Reviewed-on: https://go-review.googlesource.com/10033 Reviewed-by: Alan Donovan <adonovan@google.com>
This commit is contained in:
Keith Randall
parent
12f980bc85
commit
b3137966db
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@ -292,7 +292,7 @@ func (s *ssaState) expr(n *Node) *ssa.Value {
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case OIND:
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p := s.expr(n.Left)
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c := s.curBlock.NewValue1(ssa.OpCheckNil, ssa.TypeBool, nil, p)
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c := s.curBlock.NewValue1(ssa.OpIsNonNil, ssa.TypeBool, nil, p)
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b := s.endBlock()
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b.Kind = ssa.BlockIf
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b.Control = c
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@ -322,7 +322,7 @@ func (s *ssaState) expr(n *Node) *ssa.Value {
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// bounds check
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len := s.curBlock.NewValue1(ssa.OpSliceLen, s.config.UIntPtr, nil, a)
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cmp := s.curBlock.NewValue2(ssa.OpCheckBound, ssa.TypeBool, nil, i, len)
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cmp := s.curBlock.NewValue2(ssa.OpIsInBounds, ssa.TypeBool, nil, i, len)
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b := s.endBlock()
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b.Kind = ssa.BlockIf
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b.Control = cmp
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@ -345,7 +345,7 @@ func (s *ssaState) expr(n *Node) *ssa.Value {
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log.Fatalf("can't handle CALLFUNC with non-ONAME fn %s", opnames[n.Left.Op])
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}
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bNext := s.f.NewBlock(ssa.BlockPlain)
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call := s.curBlock.NewValue1(ssa.OpStaticCall, ssa.TypeMem, n.Left.Sym.Name, s.mem())
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call := s.curBlock.NewValue1(ssa.OpStaticCall, ssa.TypeMem, n.Left.Sym, s.mem())
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b := s.endBlock()
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b.Kind = ssa.BlockCall
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b.Control = call
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@ -209,8 +209,8 @@ func lowerAmd64(v *Value) bool {
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goto enda4e64c7eaeda16c1c0db9dac409cd126
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enda4e64c7eaeda16c1c0db9dac409cd126:
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;
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case OpCheckBound:
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// match: (CheckBound idx len)
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case OpIsInBounds:
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// match: (IsInBounds idx len)
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// cond:
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// result: (SETB (CMPQ <TypeFlags> idx len))
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{
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@ -226,11 +226,11 @@ func lowerAmd64(v *Value) bool {
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v.AddArg(v0)
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return true
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}
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goto end249426f6f996d45a62f89a591311a954
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end249426f6f996d45a62f89a591311a954:
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goto endb51d371171154c0f1613b687757e0576
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endb51d371171154c0f1613b687757e0576:
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;
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case OpCheckNil:
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// match: (CheckNil p)
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case OpIsNonNil:
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// match: (IsNonNil p)
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// cond:
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// result: (SETNE (TESTQ <TypeFlags> p p))
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{
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@ -245,8 +245,8 @@ func lowerAmd64(v *Value) bool {
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v.AddArg(v0)
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return true
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}
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goto end90d3057824f74ef953074e473aa0b282
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end90d3057824f74ef953074e473aa0b282:
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goto endff508c3726edfb573abc6128c177e76c
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endff508c3726edfb573abc6128c177e76c:
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;
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case OpLess:
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// match: (Less x y)
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@ -378,17 +378,17 @@ func lowerAmd64(v *Value) bool {
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;
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// match: (MOVQload [off1] (LEAQ8 [off2] ptr idx) mem)
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// cond:
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// result: (MOVQload8 [off1.(int64)+off2.(int64)] ptr idx mem)
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// result: (MOVQloadidx8 [off1.(int64)+off2.(int64)] ptr idx mem)
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{
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off1 := v.Aux
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if v.Args[0].Op != OpLEAQ8 {
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goto end35060118a284c93323ab3fb827156638
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goto endba0e5cee85021614041016b1a2709ab8
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}
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off2 := v.Args[0].Aux
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ptr := v.Args[0].Args[0]
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idx := v.Args[0].Args[1]
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mem := v.Args[1]
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v.Op = OpMOVQload8
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v.Op = OpMOVQloadidx8
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v.Aux = nil
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v.resetArgs()
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v.Aux = off1.(int64) + off2.(int64)
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@ -397,8 +397,8 @@ func lowerAmd64(v *Value) bool {
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v.AddArg(mem)
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return true
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}
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goto end35060118a284c93323ab3fb827156638
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end35060118a284c93323ab3fb827156638:
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goto endba0e5cee85021614041016b1a2709ab8
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endba0e5cee85021614041016b1a2709ab8:
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;
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case OpMOVQstore:
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// match: (MOVQstore [off1] (FPAddr [off2]) val mem)
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@ -493,18 +493,18 @@ func lowerAmd64(v *Value) bool {
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;
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// match: (MOVQstore [off1] (LEAQ8 [off2] ptr idx) val mem)
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// cond:
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// result: (MOVQstore8 [off1.(int64)+off2.(int64)] ptr idx val mem)
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// result: (MOVQstoreidx8 [off1.(int64)+off2.(int64)] ptr idx val mem)
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{
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off1 := v.Aux
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if v.Args[0].Op != OpLEAQ8 {
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goto endb5cba0ee3ba21d2bd8e5aa163d2b984e
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goto end4ad469f534c7369f6ac36bdace3462ad
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}
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off2 := v.Args[0].Aux
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ptr := v.Args[0].Args[0]
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idx := v.Args[0].Args[1]
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val := v.Args[1]
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mem := v.Args[2]
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v.Op = OpMOVQstore8
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v.Op = OpMOVQstoreidx8
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v.Aux = nil
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v.resetArgs()
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v.Aux = off1.(int64) + off2.(int64)
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@ -514,8 +514,8 @@ func lowerAmd64(v *Value) bool {
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v.AddArg(mem)
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return true
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}
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goto endb5cba0ee3ba21d2bd8e5aa163d2b984e
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endb5cba0ee3ba21d2bd8e5aa163d2b984e:
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goto end4ad469f534c7369f6ac36bdace3462ad
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end4ad469f534c7369f6ac36bdace3462ad:
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;
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case OpMULCQ:
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// match: (MULCQ [c] x)
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@ -8,25 +8,33 @@ package ssa
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// Opcodes' semantics can be modified by the type and aux fields of the Value.
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// For instance, OpAdd can be 32 or 64 bit, signed or unsigned, float or complex, depending on Value.Type.
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// Semantics of each op are described below.
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//
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// Ops come in two flavors, architecture-independent and architecture-dependent.
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// Architecture-independent opcodes appear in this file.
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// Architecture-dependent opcodes appear in op{arch}.go files.
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type Op int32
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// All the opcodes
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// Opcode ranges, a generic one and one for each architecture.
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const (
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OpUnknown Op = iota
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opInvalid Op = 0
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opGenericBase Op = 1 + 1000*iota
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opAMD64Base
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op386Base
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// machine-independent opcodes
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opMax // sentinel
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)
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OpNop // should never be used, appears only briefly during construction, Has type Void.
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OpFwdRef // used during ssa construction. Like OpCopy, but the arg has not been specified yet.
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// Generic opcodes
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const (
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opGenericStart Op = opGenericBase + iota
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// 2-input arithmetic
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OpAdd
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OpSub
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OpMul
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OpAdd // arg0 + arg1
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OpSub // arg0 - arg1
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OpMul // arg0 * arg1
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// 2-input comparisons
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OpLess
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OpLess // arg0 < arg1
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// constants. Constant values are stored in the aux field.
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// booleans have a bool aux field, strings have a string aux
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@ -36,44 +44,40 @@ const (
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// as it may be different widths on the host and target.
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OpConst
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OpArg // address of a function parameter/result. Memory input is an arg called ".mem".
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OpGlobal // address of a global variable (aux is a *gc.Sym)
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OpArg // address of a function parameter/result. Memory input is an arg called ".mem". aux is a string (TODO: make it something other than a string?)
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OpGlobal // the address of a global variable aux.(*gc.Sym)
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OpFunc // entry address of a function
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OpCopy // output = input
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OpPhi // select an input based on which predecessor we came from
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OpSliceMake // args are ptr/len/cap
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OpSlicePtr
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OpSliceLen
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OpSliceCap
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OpCopy // output = arg0
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OpPhi // select an argument based on which predecessor block we came from
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OpStringMake // args are ptr/len
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OpStringPtr
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OpStringLen
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OpSliceMake // arg0=ptr, arg1=len, arg2=cap
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OpSlicePtr // ptr(arg0)
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OpSliceLen // len(arg0)
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OpSliceCap // cap(arg0)
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OpSliceIndex
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OpSliceIndexAddr
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OpStringMake // arg0=ptr, arg1=len
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OpStringPtr // ptr(arg0)
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OpStringLen // len(arg0)
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OpLoad // args are ptr, memory. Loads from ptr+aux.(int64)
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OpStore // args are ptr, value, memory, returns memory. Stores to ptr+aux.(int64)
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OpCheckNil // arg[0] != nil
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OpCheckBound // 0 <= arg[0] < arg[1]
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OpLoad // Load from arg0+aux.(int64). arg1=memory
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OpStore // Store arg1 to arg0+aux.(int64). arg2=memory. Returns memory.
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OpSliceIndex // arg0=slice, arg1=index, arg2=memory
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OpIsNonNil // arg0 != nil
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OpIsInBounds // 0 <= arg0 < arg1
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// function calls. Arguments to the call have already been written to the stack.
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// Return values appear on the stack. The method receiver, if any, is treated
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// as a phantom first argument.
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// TODO: closure pointer must be in a register.
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OpCall // args are function ptr, memory
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OpStaticCall // aux is function, arg is memory
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OpCall // arg0=code pointer, arg1=context ptr, arg2=memory. Returns memory.
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OpStaticCall // call function aux.(*gc.Sym), arg0=memory. Returns memory.
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OpConvert
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OpConvNop
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OpConvert // convert arg0 to another type
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OpConvNop // interpret arg0 as another type
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// These ops return a pointer to a location on the stack. Aux contains an int64
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// indicating an offset from the base pointer.
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OpFPAddr // offset from FP (+ == args from caller, - == locals)
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OpSPAddr // offset from SP
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// These ops return a pointer to a location on the stack.
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OpFPAddr // FP + aux.(int64) (+ == args from caller, - == locals)
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OpSPAddr // SP + aux.(int64)
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// spill&restore ops for the register allocator. These are
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// semantically identical to OpCopy; they do not take/return
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@ -82,70 +86,19 @@ const (
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OpStoreReg8
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OpLoadReg8
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// machine-dependent opcodes go here
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// amd64
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OpADDQ
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OpSUBQ
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OpADDCQ // 1 input arg. output = input + aux.(int64)
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OpSUBCQ // 1 input arg. output = input - aux.(int64)
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OpMULQ
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OpMULCQ // output = input * aux.(int64)
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OpSHLQ // output = input0 << input1
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OpSHLCQ // output = input << aux.(int64)
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OpNEGQ
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OpCMPQ
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OpCMPCQ // 1 input arg. Compares input with aux.(int64)
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OpADDL
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OpTESTQ // compute flags of arg[0] & arg[1]
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OpSETEQ
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OpSETNE
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// generate boolean based on the flags setting
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OpSETL // less than
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OpSETGE // >=
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OpSETB // "below" = unsigned less than
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// InvertFlags reverses direction of flags register interpretation:
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// (InvertFlags (OpCMPQ a b)) == (OpCMPQ b a)
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// This is a pseudo-op which can't appear in assembly output.
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OpInvertFlags
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OpLEAQ // x+y
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OpLEAQ2 // x+2*y
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OpLEAQ4 // x+4*y
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OpLEAQ8 // x+8*y
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OpMOVQload // (ptr, mem): loads from ptr+aux.(int64)
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OpMOVQstore // (ptr, val, mem): stores val to ptr+aux.(int64), returns mem
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OpMOVQload8 // (ptr,idx,mem): loads from ptr+idx*8+aux.(int64)
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OpMOVQstore8 // (ptr,idx,val,mem): stores to ptr+idx*8+aux.(int64), returns mem
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// load/store from global. aux = GlobalOffset
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OpMOVQloadglobal // (mem) -> value
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OpMOVQstoreglobal // (val, mem) -> mem
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// load/store 8-byte integer register from stack slot.
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OpMOVQloadFP
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OpMOVQloadSP
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OpMOVQstoreFP
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OpMOVQstoreSP
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// materialize a constant into a register
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OpMOVQconst
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OpMax // sentinel
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// used during ssa construction. Like OpCopy, but the arg has not been specified yet.
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OpFwdRef
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)
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// GlobalOffset represents a fixed offset within a global variable
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type GlobalOffset struct {
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Global interface{} // holds a *cmd/internal/gc.Sym
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Global interface{} // holds a *gc.Sym
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Offset int64
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}
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//go:generate stringer -type=Op
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type OpInfo struct {
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type opInfo struct {
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flags int32
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// assembly template
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@ -160,67 +113,13 @@ type OpInfo struct {
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reg [2][]regMask
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}
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type regMask uint64
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var regs386 = [...]string{
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"AX",
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"CX",
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"DX",
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"BX",
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"SP",
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"BP",
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"SI",
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"DI",
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// pseudo registers
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"FLAGS",
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"OVERWRITE0", // the same register as the first input
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}
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// TODO: match up these with regs386 above
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var gp regMask = 0xef
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var cx regMask = 0x2
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var flags regMask = 1 << 8
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var overwrite0 regMask = 1 << 9
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const (
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// possible properties of opcodes
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OpFlagCommutative int32 = 1 << iota
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// architecture constants
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Arch386
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ArchAMD64
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ArchARM
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)
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// general purpose registers, 2 input, 1 output
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var gp21 = [2][]regMask{{gp, gp}, {gp}}
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var gp21_overwrite = [2][]regMask{{gp, gp}, {gp}}
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// general purpose registers, 1 input, 1 output
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var gp11 = [2][]regMask{{gp}, {gp}}
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var gp11_overwrite = [2][]regMask{{gp}, {gp}}
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// general purpose registers, 0 input, 1 output
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var gp01 = [2][]regMask{{}, {gp}}
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// shift operations
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var shift = [2][]regMask{{gp, cx}, {gp}}
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var gp2_flags = [2][]regMask{{gp, gp}, {flags}}
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var gp1_flags = [2][]regMask{{gp}, {flags}}
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var gpload = [2][]regMask{{gp, 0}, {gp}}
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var gploadX = [2][]regMask{{gp, gp, 0}, {gp}} // indexed loads
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var gpstore = [2][]regMask{{gp, gp, 0}, {0}}
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var gpstoreX = [2][]regMask{{gp, gp, gp, 0}, {0}} // indexed stores
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var gploadglobal = [2][]regMask{{0}, {gp}}
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var gpstoreglobal = [2][]regMask{{gp, 0}, {0}}
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var gpload_stack = [2][]regMask{{0}, {gp}}
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var gpstore_stack = [2][]regMask{{gp, 0}, {0}}
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// Opcodes that represent the input Go program
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var genericTable = [...]OpInfo{
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var genericTable = map[Op]opInfo{
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// the unknown op is used only during building and should not appear in a
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// fully formed ssa representation.
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@ -278,87 +177,11 @@ var genericTable = [...]OpInfo{
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*/
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}
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// Opcodes that appear in an output amd64 program
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var amd64Table = [...]OpInfo{
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OpADDQ: {flags: OpFlagCommutative, asm: "ADDQ\t%I0,%I1,%O0", reg: gp21}, // TODO: overwrite
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OpADDCQ: {asm: "ADDQ\t$%A,%I0,%O0", reg: gp11_overwrite}, // aux = int64 constant to add
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OpSUBQ: {asm: "SUBQ\t%I0,%I1,%O0", reg: gp21},
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OpSUBCQ: {asm: "SUBQ\t$%A,%I0,%O0", reg: gp11_overwrite},
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OpMULQ: {asm: "MULQ\t%I0,%I1,%O0", reg: gp21},
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OpMULCQ: {asm: "MULQ\t$%A,%I0,%O0", reg: gp11_overwrite},
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OpSHLQ: {asm: "SHLQ\t%I0,%I1,%O0", reg: gp21},
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OpSHLCQ: {asm: "SHLQ\t$%A,%I0,%O0", reg: gp11_overwrite},
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OpCMPQ: {asm: "CMPQ\t%I0,%I1", reg: gp2_flags}, // compute arg[0]-arg[1] and produce flags
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OpCMPCQ: {asm: "CMPQ\t$%A,%I0", reg: gp1_flags},
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OpTESTQ: {asm: "TESTQ\t%I0,%I1", reg: gp2_flags},
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OpLEAQ: {flags: OpFlagCommutative, asm: "LEAQ\t%A(%I0)(%I1*1),%O0", reg: gp21}, // aux = int64 constant to add
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OpLEAQ2: {asm: "LEAQ\t%A(%I0)(%I1*2),%O0"},
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OpLEAQ4: {asm: "LEAQ\t%A(%I0)(%I1*4),%O0"},
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OpLEAQ8: {asm: "LEAQ\t%A(%I0)(%I1*8),%O0"},
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// loads and stores
|
||||
OpMOVQload: {asm: "MOVQ\t%A(%I0),%O0", reg: gpload},
|
||||
OpMOVQstore: {asm: "MOVQ\t%I1,%A(%I0)", reg: gpstore},
|
||||
OpMOVQload8: {asm: "MOVQ\t%A(%I0)(%I1*8),%O0", reg: gploadX},
|
||||
OpMOVQstore8: {asm: "MOVQ\t%I2,%A(%I0)(%I1*8)", reg: gpstoreX},
|
||||
|
||||
OpMOVQloadglobal: {reg: gploadglobal},
|
||||
OpMOVQstoreglobal: {reg: gpstoreglobal},
|
||||
|
||||
OpMOVQconst: {asm: "MOVQ\t$%A,%O0", reg: gp01},
|
||||
|
||||
OpStaticCall: {asm: "CALL\t%A(SB)"},
|
||||
|
||||
OpCopy: {asm: "MOVQ\t%I0,%O0", reg: gp11},
|
||||
|
||||
// convert from flags back to boolean
|
||||
OpSETL: {},
|
||||
|
||||
// ops for load/store to stack
|
||||
OpMOVQloadFP: {asm: "MOVQ\t%A(FP),%O0", reg: gpload_stack}, // mem -> value
|
||||
OpMOVQloadSP: {asm: "MOVQ\t%A(SP),%O0", reg: gpload_stack}, // mem -> value
|
||||
OpMOVQstoreFP: {asm: "MOVQ\t%I0,%A(FP)", reg: gpstore_stack}, // mem, value -> mem
|
||||
OpMOVQstoreSP: {asm: "MOVQ\t%I0,%A(SP)", reg: gpstore_stack}, // mem, value -> mem
|
||||
|
||||
// ops for spilling of registers
|
||||
// unlike regular loads & stores, these take no memory argument.
|
||||
// They are just like OpCopy but we use them during register allocation.
|
||||
// TODO: different widths, float
|
||||
OpLoadReg8: {asm: "MOVQ\t%I0,%O0"},
|
||||
OpStoreReg8: {asm: "MOVQ\t%I0,%O0"},
|
||||
}
|
||||
|
||||
// A Table is a list of opcodes with a common set of flags.
|
||||
type Table struct {
|
||||
t []OpInfo
|
||||
flags int32
|
||||
}
|
||||
|
||||
var tables = []Table{
|
||||
{genericTable[:], 0},
|
||||
{amd64Table[:], ArchAMD64}, // TODO: pick this dynamically
|
||||
}
|
||||
|
||||
// table of opcodes, indexed by opcode ID
|
||||
var opcodeTable [OpMax]OpInfo
|
||||
|
||||
// map from opcode names to opcode IDs
|
||||
var nameToOp map[string]Op
|
||||
var opcodeTable [opMax]opInfo
|
||||
|
||||
func init() {
|
||||
// build full opcode table
|
||||
// Note that the arch-specific table overwrites the generic table
|
||||
for _, t := range tables {
|
||||
for op, entry := range t.t {
|
||||
entry.flags |= t.flags
|
||||
opcodeTable[op] = entry
|
||||
}
|
||||
}
|
||||
// build name to opcode mapping
|
||||
nameToOp = make(map[string]Op)
|
||||
for op := range opcodeTable {
|
||||
nameToOp[Op(op).String()] = Op(op)
|
||||
for op, info := range genericTable {
|
||||
opcodeTable[op] = info
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,13 +4,37 @@ package ssa
|
|||
|
||||
import "fmt"
|
||||
|
||||
const _Op_name = "OpUnknownOpNopOpFwdRefOpAddOpSubOpMulOpLessOpConstOpArgOpGlobalOpFuncOpCopyOpPhiOpSliceMakeOpSlicePtrOpSliceLenOpSliceCapOpStringMakeOpStringPtrOpStringLenOpSliceIndexOpSliceIndexAddrOpLoadOpStoreOpCheckNilOpCheckBoundOpCallOpStaticCallOpConvertOpConvNopOpFPAddrOpSPAddrOpStoreReg8OpLoadReg8OpADDQOpSUBQOpADDCQOpSUBCQOpMULQOpMULCQOpSHLQOpSHLCQOpNEGQOpCMPQOpCMPCQOpADDLOpTESTQOpSETEQOpSETNEOpSETLOpSETGEOpSETBOpInvertFlagsOpLEAQOpLEAQ2OpLEAQ4OpLEAQ8OpMOVQloadOpMOVQstoreOpMOVQload8OpMOVQstore8OpMOVQloadglobalOpMOVQstoreglobalOpMOVQloadFPOpMOVQloadSPOpMOVQstoreFPOpMOVQstoreSPOpMOVQconstOpMax"
|
||||
const (
|
||||
_Op_name_0 = "opInvalid"
|
||||
_Op_name_1 = "opGenericBaseOpAddOpSubOpMulOpLessOpConstOpArgOpGlobalOpFuncOpCopyOpPhiOpSliceMakeOpSlicePtrOpSliceLenOpSliceCapOpStringMakeOpStringPtrOpStringLenOpLoadOpStoreOpSliceIndexOpIsNonNilOpIsInBoundsOpCallOpStaticCallOpConvertOpConvNopOpFPAddrOpSPAddrOpStoreReg8OpLoadReg8OpFwdRef"
|
||||
_Op_name_2 = "opAMD64BaseOpADDQOpSUBQOpADDCQOpSUBCQOpMULQOpMULCQOpSHLQOpSHLCQOpNEGQOpADDLOpCMPQOpCMPCQOpTESTQOpSETEQOpSETNEOpSETLOpSETGEOpSETBOpInvertFlagsOpLEAQOpLEAQ2OpLEAQ4OpLEAQ8OpMOVQloadOpMOVQstoreOpMOVQloadidx8OpMOVQstoreidx8OpMOVQloadglobalOpMOVQstoreglobalOpMOVQloadFPOpMOVQloadSPOpMOVQstoreFPOpMOVQstoreSPOpMOVQconst"
|
||||
_Op_name_3 = "op386Base"
|
||||
_Op_name_4 = "opMax"
|
||||
)
|
||||
|
||||
var _Op_index = [...]uint16{0, 9, 14, 22, 27, 32, 37, 43, 50, 55, 63, 69, 75, 80, 91, 101, 111, 121, 133, 144, 155, 167, 183, 189, 196, 206, 218, 224, 236, 245, 254, 262, 270, 281, 291, 297, 303, 310, 317, 323, 330, 336, 343, 349, 355, 362, 368, 375, 382, 389, 395, 402, 408, 421, 427, 434, 441, 448, 458, 469, 480, 492, 508, 525, 537, 549, 562, 575, 586, 591}
|
||||
var (
|
||||
_Op_index_0 = [...]uint8{0, 9}
|
||||
_Op_index_1 = [...]uint16{0, 13, 18, 23, 28, 34, 41, 46, 54, 60, 66, 71, 82, 92, 102, 112, 124, 135, 146, 152, 159, 171, 181, 193, 199, 211, 220, 229, 237, 245, 256, 266, 274}
|
||||
_Op_index_2 = [...]uint16{0, 11, 17, 23, 30, 37, 43, 50, 56, 63, 69, 75, 81, 88, 95, 102, 109, 115, 122, 128, 141, 147, 154, 161, 168, 178, 189, 203, 218, 234, 251, 263, 275, 288, 301, 312}
|
||||
_Op_index_3 = [...]uint8{0, 9}
|
||||
_Op_index_4 = [...]uint8{0, 5}
|
||||
)
|
||||
|
||||
func (i Op) String() string {
|
||||
if i < 0 || i+1 >= Op(len(_Op_index)) {
|
||||
switch {
|
||||
case i == 0:
|
||||
return _Op_name_0
|
||||
case 1001 <= i && i <= 1032:
|
||||
i -= 1001
|
||||
return _Op_name_1[_Op_index_1[i]:_Op_index_1[i+1]]
|
||||
case 2001 <= i && i <= 2035:
|
||||
i -= 2001
|
||||
return _Op_name_2[_Op_index_2[i]:_Op_index_2[i+1]]
|
||||
case i == 3001:
|
||||
return _Op_name_3
|
||||
case i == 4001:
|
||||
return _Op_name_4
|
||||
default:
|
||||
return fmt.Sprintf("Op(%d)", i)
|
||||
}
|
||||
return _Op_name[_Op_index[i]:_Op_index[i+1]]
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,171 @@
|
|||
// Copyright 2015 The Go Authors. All rights reserved.
|
||||
// Use of this source code is governed by a BSD-style
|
||||
// license that can be found in the LICENSE file.
|
||||
|
||||
package ssa
|
||||
|
||||
// amd64-specific opcodes
|
||||
|
||||
const (
|
||||
opAMD64start Op = opAMD64Base + iota
|
||||
|
||||
// Suffixes encode the bit width of various instructions.
|
||||
// Q = 64 bit, L = 32 bit, W = 16 bit, B = 8 bit
|
||||
|
||||
// arithmetic
|
||||
OpADDQ // arg0 + arg1
|
||||
OpSUBQ // arg0 - arg1
|
||||
OpADDCQ // arg + aux.(int64)
|
||||
OpSUBCQ // arg - aux.(int64)
|
||||
OpMULQ // arg0 * arg1
|
||||
OpMULCQ // arg * aux.(int64)
|
||||
OpSHLQ // arg0 << arg1
|
||||
OpSHLCQ // arg << aux.(int64)
|
||||
OpNEGQ // -arg
|
||||
OpADDL // arg0 + arg1
|
||||
|
||||
// Flags value generation.
|
||||
// We pretend the flags type is an opaque thing that comparisons generate
|
||||
// and from which we can extract boolean conditions like <, ==, etc.
|
||||
OpCMPQ // arg0 compare to arg1
|
||||
OpCMPCQ // arg0 compare to aux.(int64)
|
||||
OpTESTQ // (arg0 & arg1) compare to 0
|
||||
|
||||
// These opcodes extract a particular boolean condition from a flags value.
|
||||
OpSETEQ // extract == condition from arg0
|
||||
OpSETNE // extract != condition from arg0
|
||||
OpSETL // extract signed < condition from arg0
|
||||
OpSETGE // extract signed >= condition from arg0
|
||||
OpSETB // extract unsigned < condition from arg0
|
||||
|
||||
// InvertFlags reverses the direction of a flags type interpretation:
|
||||
// (InvertFlags (OpCMPQ a b)) == (OpCMPQ b a)
|
||||
// This is a pseudo-op which can't appear in assembly output.
|
||||
OpInvertFlags // reverse direction of arg0
|
||||
|
||||
OpLEAQ // arg0 + arg1 + aux.(int64)
|
||||
OpLEAQ2 // arg0 + 2*arg1 + aux.(int64)
|
||||
OpLEAQ4 // arg0 + 4*arg1 + aux.(int64)
|
||||
OpLEAQ8 // arg0 + 8*arg1 + aux.(int64)
|
||||
|
||||
// Load/store from general address
|
||||
OpMOVQload // Load from arg0+aux.(int64). arg1=memory
|
||||
OpMOVQstore // Store arg1 to arg0+aux.(int64). arg2=memory, returns memory.
|
||||
OpMOVQloadidx8 // Load from arg0+arg1*8+aux.(int64). arg2=memory
|
||||
OpMOVQstoreidx8 // Store arg2 to arg0+arg1*8+aux.(int64). arg3=memory, returns memory.
|
||||
|
||||
// Load/store from global. aux.(GlobalOffset) encodes the global location.
|
||||
OpMOVQloadglobal // arg0 = memory
|
||||
OpMOVQstoreglobal // store arg0. arg1=memory, returns memory.
|
||||
|
||||
// Load/store from stack slot.
|
||||
OpMOVQloadFP // load from FP+aux.(int64). arg0=memory
|
||||
OpMOVQloadSP // load from SP+aux.(int64). arg0=memory
|
||||
OpMOVQstoreFP // store arg0 to FP+aux.(int64). arg1=memory, returns memory.
|
||||
OpMOVQstoreSP // store arg0 to SP+aux.(int64). arg1=memory, returns memory.
|
||||
|
||||
// materialize a constant into a register
|
||||
OpMOVQconst // (takes no arguments)
|
||||
)
|
||||
|
||||
type regMask uint64
|
||||
|
||||
var regsAMD64 = [...]string{
|
||||
"AX",
|
||||
"CX",
|
||||
"DX",
|
||||
"BX",
|
||||
"SP",
|
||||
"BP",
|
||||
"SI",
|
||||
"DI",
|
||||
"R8",
|
||||
"R9",
|
||||
"R10",
|
||||
"R11",
|
||||
"R12",
|
||||
"R13",
|
||||
"R14",
|
||||
"R15",
|
||||
|
||||
// pseudo registers
|
||||
"FLAGS",
|
||||
"OVERWRITE0", // the same register as the first input
|
||||
}
|
||||
|
||||
var gp regMask = 0xef // all integer registers except SP
|
||||
var cx regMask = 0x2
|
||||
var flags regMask = 1 << 16
|
||||
|
||||
var (
|
||||
// gp = general purpose (integer) registers
|
||||
gp21 = [2][]regMask{{gp, gp}, {gp}} // 2 input, 1 output
|
||||
gp11 = [2][]regMask{{gp}, {gp}} // 1 input, 1 output
|
||||
gp01 = [2][]regMask{{}, {gp}} // 0 input, 1 output
|
||||
shift = [2][]regMask{{gp, cx}, {gp}} // shift operations
|
||||
gp2_flags = [2][]regMask{{gp, gp}, {flags}} // generate flags from 2 gp regs
|
||||
gp1_flags = [2][]regMask{{gp}, {flags}} // generate flags from 1 gp reg
|
||||
|
||||
gpload = [2][]regMask{{gp, 0}, {gp}}
|
||||
gploadidx = [2][]regMask{{gp, gp, 0}, {gp}}
|
||||
gpstore = [2][]regMask{{gp, gp, 0}, {0}}
|
||||
gpstoreidx = [2][]regMask{{gp, gp, gp, 0}, {0}}
|
||||
|
||||
gpload_stack = [2][]regMask{{0}, {gp}}
|
||||
gpstore_stack = [2][]regMask{{gp, 0}, {0}}
|
||||
)
|
||||
|
||||
// Opcodes that appear in an output amd64 program
|
||||
var amd64Table = map[Op]opInfo{
|
||||
OpADDQ: {flags: OpFlagCommutative, asm: "ADDQ\t%I0,%I1,%O0", reg: gp21}, // TODO: overwrite
|
||||
OpADDCQ: {asm: "ADDQ\t$%A,%I0,%O0", reg: gp11}, // aux = int64 constant to add
|
||||
OpSUBQ: {asm: "SUBQ\t%I0,%I1,%O0", reg: gp21},
|
||||
OpSUBCQ: {asm: "SUBQ\t$%A,%I0,%O0", reg: gp11},
|
||||
OpMULQ: {asm: "MULQ\t%I0,%I1,%O0", reg: gp21},
|
||||
OpMULCQ: {asm: "MULQ\t$%A,%I0,%O0", reg: gp11},
|
||||
OpSHLQ: {asm: "SHLQ\t%I0,%I1,%O0", reg: gp21},
|
||||
OpSHLCQ: {asm: "SHLQ\t$%A,%I0,%O0", reg: gp11},
|
||||
|
||||
OpCMPQ: {asm: "CMPQ\t%I0,%I1", reg: gp2_flags}, // compute arg[0]-arg[1] and produce flags
|
||||
OpCMPCQ: {asm: "CMPQ\t$%A,%I0", reg: gp1_flags},
|
||||
OpTESTQ: {asm: "TESTQ\t%I0,%I1", reg: gp2_flags},
|
||||
|
||||
OpLEAQ: {flags: OpFlagCommutative, asm: "LEAQ\t%A(%I0)(%I1*1),%O0", reg: gp21}, // aux = int64 constant to add
|
||||
OpLEAQ2: {asm: "LEAQ\t%A(%I0)(%I1*2),%O0"},
|
||||
OpLEAQ4: {asm: "LEAQ\t%A(%I0)(%I1*4),%O0"},
|
||||
OpLEAQ8: {asm: "LEAQ\t%A(%I0)(%I1*8),%O0"},
|
||||
|
||||
// loads and stores
|
||||
OpMOVQload: {asm: "MOVQ\t%A(%I0),%O0", reg: gpload},
|
||||
OpMOVQstore: {asm: "MOVQ\t%I1,%A(%I0)", reg: gpstore},
|
||||
OpMOVQloadidx8: {asm: "MOVQ\t%A(%I0)(%I1*8),%O0", reg: gploadidx},
|
||||
OpMOVQstoreidx8: {asm: "MOVQ\t%I2,%A(%I0)(%I1*8)", reg: gpstoreidx},
|
||||
|
||||
OpMOVQconst: {asm: "MOVQ\t$%A,%O0", reg: gp01},
|
||||
|
||||
OpStaticCall: {asm: "CALL\t%A(SB)"},
|
||||
|
||||
OpCopy: {asm: "MOVQ\t%I0,%O0", reg: gp11},
|
||||
|
||||
// convert from flags back to boolean
|
||||
OpSETL: {},
|
||||
|
||||
// ops for load/store to stack
|
||||
OpMOVQloadFP: {asm: "MOVQ\t%A(FP),%O0", reg: gpload_stack}, // mem -> value
|
||||
OpMOVQloadSP: {asm: "MOVQ\t%A(SP),%O0", reg: gpload_stack}, // mem -> value
|
||||
OpMOVQstoreFP: {asm: "MOVQ\t%I0,%A(FP)", reg: gpstore_stack}, // mem, value -> mem
|
||||
OpMOVQstoreSP: {asm: "MOVQ\t%I0,%A(SP)", reg: gpstore_stack}, // mem, value -> mem
|
||||
|
||||
// ops for spilling of registers
|
||||
// unlike regular loads & stores, these take no memory argument.
|
||||
// They are just like OpCopy but we use them during register allocation.
|
||||
// TODO: different widths, float
|
||||
OpLoadReg8: {asm: "MOVQ\t%I0,%O0"},
|
||||
OpStoreReg8: {asm: "MOVQ\t%I0,%O0"},
|
||||
}
|
||||
|
||||
func init() {
|
||||
for op, info := range amd64Table {
|
||||
opcodeTable[op] = info
|
||||
}
|
||||
}
|
||||
|
|
@ -28,8 +28,16 @@ var registers = [...]Register{
|
|||
Register{"BP"},
|
||||
Register{"SI"},
|
||||
Register{"DI"},
|
||||
Register{"R8"},
|
||||
Register{"R9"},
|
||||
Register{"R10"},
|
||||
Register{"R11"},
|
||||
Register{"R12"},
|
||||
Register{"R13"},
|
||||
Register{"R14"},
|
||||
Register{"R15"},
|
||||
|
||||
// TODO R8, X0, ...
|
||||
// TODO X0, ...
|
||||
// TODO: make arch-dependent
|
||||
Register{"FLAGS"},
|
||||
Register{"OVERWRITE"},
|
||||
|
|
|
|||
|
|
@ -34,8 +34,8 @@
|
|||
(Store ptr val mem) && (is64BitInt(val.Type) || isPtr(val.Type)) -> (MOVQstore [int64(0)] ptr val mem)
|
||||
|
||||
// checks
|
||||
(CheckNil p) -> (SETNE (TESTQ <TypeFlags> p p))
|
||||
(CheckBound idx len) -> (SETB (CMPQ <TypeFlags> idx len))
|
||||
(IsNonNil p) -> (SETNE (TESTQ <TypeFlags> p p))
|
||||
(IsInBounds idx len) -> (SETB (CMPQ <TypeFlags> idx len))
|
||||
|
||||
// Rules below here apply some simple optimizations after lowering.
|
||||
// TODO: Should this be a separate pass?
|
||||
|
|
@ -80,8 +80,8 @@
|
|||
(MOVQstore [off1] (ADDCQ [off2] ptr) val mem) -> (MOVQstore [off1.(int64)+off2.(int64)] ptr val mem)
|
||||
|
||||
// indexed loads and stores
|
||||
(MOVQload [off1] (LEAQ8 [off2] ptr idx) mem) -> (MOVQload8 [off1.(int64)+off2.(int64)] ptr idx mem)
|
||||
(MOVQstore [off1] (LEAQ8 [off2] ptr idx) val mem) -> (MOVQstore8 [off1.(int64)+off2.(int64)] ptr idx val mem)
|
||||
(MOVQload [off1] (LEAQ8 [off2] ptr idx) mem) -> (MOVQloadidx8 [off1.(int64)+off2.(int64)] ptr idx mem)
|
||||
(MOVQstore [off1] (LEAQ8 [off2] ptr idx) val mem) -> (MOVQstoreidx8 [off1.(int64)+off2.(int64)] ptr idx val mem)
|
||||
|
||||
// Combine the offset of a stack object with the offset within a stack object
|
||||
(ADDCQ [off1] (FPAddr [off2])) -> (FPAddr [off1.(int64)+off2.(int64)])
|
||||
|
|
|
|||
Loading…
Reference in New Issue