mirror of https://github.com/golang/go.git
cmd/5g: factor out prog information
Like CL 12637051, but for 5g instead of 6g. R=ken2 CC=golang-dev https://golang.org/cl/12779043
This commit is contained in:
Russ Cox
parent
5636b60b70
commit
a07218385c
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@ -165,3 +165,55 @@ int32 RtoB(int);
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int32 FtoB(int);
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int BtoR(int32);
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int BtoF(int32);
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/*
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* prog.c
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*/
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typedef struct ProgInfo ProgInfo;
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struct ProgInfo
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{
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uint32 flags; // the bits below
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};
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enum
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{
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// Pseudo-op, like TEXT, GLOBL, TYPE, PCDATA, FUNCDATA.
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Pseudo = 1<<1,
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// There's nothing to say about the instruction,
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// but it's still okay to see.
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OK = 1<<2,
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// Size of right-side write, or right-side read if no write.
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SizeB = 1<<3,
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SizeW = 1<<4,
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SizeL = 1<<5,
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SizeQ = 1<<6,
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SizeF = 1<<7, // float aka float32
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SizeD = 1<<8, // double aka float64
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// Left side: address taken, read, write.
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LeftAddr = 1<<9,
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LeftRead = 1<<10,
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LeftWrite = 1<<11,
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// Register in middle; never written.
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RegRead = 1<<12,
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CanRegRead = 1<<13,
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// Right side: address taken, read, write.
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RightAddr = 1<<14,
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RightRead = 1<<15,
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RightWrite = 1<<16,
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// Instruction kinds
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Move = 1<<17, // straight move
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Conv = 1<<18, // size conversion
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Cjmp = 1<<19, // conditional jump
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Break = 1<<20, // breaks control flow (no fallthrough)
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Call = 1<<21, // function call
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Jump = 1<<22, // jump
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Skip = 1<<23, // data instruction
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};
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void proginfo(ProgInfo*, Prog*);
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@ -50,6 +50,7 @@ peep(void)
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Reg *r, *r1, *r2;
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Prog *p;
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int t;
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ProgInfo info;
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/*
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* complete R structure
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@ -58,28 +59,24 @@ peep(void)
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r1 = r->link;
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if(r1 == R)
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break;
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p = r->prog->link;
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while(p != r1->prog)
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switch(p->as) {
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default:
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for(p = r->prog->link; p != r1->prog; p = p->link) {
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proginfo(&info, p);
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if(info.flags & Skip)
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continue;
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r2 = rega();
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r->link = r2;
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r2->link = r1;
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r2->prog = p;
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p->regp = r2;
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r2->p1 = r;
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r->s1 = r2;
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r2->s1 = r1;
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r1->p1 = r2;
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r = r2;
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case ADATA:
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case AGLOBL:
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case ANAME:
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case ASIGNAME:
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case ATYPE:
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p = p->link;
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}
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}
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//dumpit("begin", firstr);
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@ -324,6 +321,7 @@ subprop(Reg *r0)
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Adr *v1, *v2;
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Reg *r;
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int t;
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ProgInfo info;
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p = r0->prog;
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v1 = &p->from;
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@ -336,68 +334,30 @@ subprop(Reg *r0)
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if(uniqs(r) == R)
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break;
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p = r->prog;
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switch(p->as) {
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case ABL:
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proginfo(&info, p);
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if(info.flags & Call)
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return 0;
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if((info.flags & CanRegRead) && p->to.type == D_REG) {
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info.flags |= RegRead;
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info.flags &= ~(CanRegRead | RightRead);
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p->reg = p->to.reg;
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}
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switch(p->as) {
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case AMULLU:
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case AMULA:
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case AMVN:
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return 0;
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case ACMN:
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case AADD:
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case ASUB:
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case ASBC:
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case ARSB:
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case ASLL:
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case ASRL:
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case ASRA:
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case AORR:
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case AAND:
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case AEOR:
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case AMUL:
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case AMULU:
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case ADIV:
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case ADIVU:
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case AMOD:
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case AMODU:
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case AADDD:
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case AADDF:
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case ASUBD:
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case ASUBF:
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case AMULD:
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case AMULF:
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case ADIVD:
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case ADIVF:
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if(p->to.type == v1->type)
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if(p->to.reg == v1->reg)
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if(p->scond == C_SCOND_NONE) {
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if(p->reg == NREG)
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p->reg = p->to.reg;
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goto gotit;
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}
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break;
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case AMOVF:
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case AMOVD:
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case AMOVB:
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case AMOVH:
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case AMOVW:
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}
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if((info.flags & (RightRead|RightWrite)) == RightWrite) {
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if(p->to.type == v1->type)
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if(p->to.reg == v1->reg)
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if(p->scond == C_SCOND_NONE)
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goto gotit;
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break;
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case AMOVM:
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t = 1<<v2->reg;
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if((p->from.type == D_CONST && (p->from.offset&t)) ||
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(p->to.type == D_CONST && (p->to.offset&t)))
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return 0;
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break;
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}
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if(copyau(&p->from, v2) ||
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copyau1(p, v2) ||
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copyau(&p->to, v2))
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@ -0,0 +1,135 @@
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// Copyright 2013 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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#include <u.h>
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#include <libc.h>
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#include "gg.h"
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#include "opt.h"
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enum
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{
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RightRdwr = RightRead | RightWrite,
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};
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// This table gives the basic information about instruction
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// generated by the compiler and processed in the optimizer.
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// See opt.h for bit definitions.
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//
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// Instructions not generated need not be listed.
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// As an exception to that rule, we typically write down all the
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// size variants of an operation even if we just use a subset.
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//
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// The table is formatted for 8-space tabs.
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static ProgInfo progtable[ALAST] = {
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[ATYPE]= {Pseudo | Skip},
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[ATEXT]= {Pseudo},
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[AFUNCDATA]= {Pseudo},
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[APCDATA]= {Pseudo},
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// NOP is an internal no-op that also stands
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// for USED and SET annotations, not the Intel opcode.
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[ANOP]= {LeftRead | RightWrite},
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// Integer.
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[AADC]= {SizeL | LeftRead | RegRead | RightWrite},
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[AADD]= {SizeL | LeftRead | RegRead | RightWrite},
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[AAND]= {SizeL | LeftRead | RegRead | RightWrite},
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[ABIC]= {SizeL | LeftRead | RegRead | RightWrite},
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[ACMN]= {SizeL | LeftRead | RightRead},
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[ACMP]= {SizeL | LeftRead | RightRead},
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[ADIVU]= {SizeL | LeftRead | RegRead | RightWrite},
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[ADIV]= {SizeL | LeftRead | RegRead | RightWrite},
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[AEOR]= {SizeL | LeftRead | RegRead | RightWrite},
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[AMODU]= {SizeL | LeftRead | RegRead | RightWrite},
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[AMOD]= {SizeL | LeftRead | RegRead | RightWrite},
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[AMULALU]= {SizeL | LeftRead | RegRead | RightRdwr},
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[AMULAL]= {SizeL | LeftRead | RegRead | RightRdwr},
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[AMULA]= {SizeL | LeftRead | RegRead | RightRdwr},
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[AMULU]= {SizeL | LeftRead | RegRead | RightWrite},
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[AMUL]= {SizeL | LeftRead | RegRead | RightWrite},
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[AMULL]= {SizeL | LeftRead | RegRead | RightWrite},
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[AMULLU]= {SizeL | LeftRead | RegRead | RightWrite},
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[AMVN]= {SizeL | LeftRead | RightWrite},
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[AORR]= {SizeL | LeftRead | RegRead | RightWrite},
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[ARSB]= {SizeL | LeftRead | RegRead | RightWrite},
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[ARSC]= {SizeL | LeftRead | RegRead | RightWrite},
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[ASBC]= {SizeL | LeftRead | RegRead | RightWrite},
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[ASLL]= {SizeL | LeftRead | RegRead | RightWrite},
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[ASRA]= {SizeL | LeftRead | RegRead | RightWrite},
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[ASRL]= {SizeL | LeftRead | RegRead | RightWrite},
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[ASUB]= {SizeL | LeftRead | RegRead | RightWrite},
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[ATEQ]= {SizeL | LeftRead | RightRead},
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[ATST]= {SizeL | LeftRead | RightRead},
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// Floating point.
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[AADDD]= {SizeD | LeftRead | RightRdwr},
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[AADDF]= {SizeF | LeftRead | RightRdwr},
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[ACMPD]= {SizeD | LeftRead | RightRead},
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[ACMPF]= {SizeF | LeftRead | RightRead},
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[ADIVD]= {SizeD | LeftRead | RightRdwr},
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[ADIVF]= {SizeF | LeftRead | RightRdwr},
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[AMULD]= {SizeD | LeftRead | RightRdwr},
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[AMULF]= {SizeF | LeftRead | RightRdwr},
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[ASUBD]= {SizeD | LeftRead | RightRdwr},
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[ASUBF]= {SizeF | LeftRead | RightRdwr},
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// Conversions.
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[AMOVWD]= {SizeD | LeftRead | RightWrite | Conv},
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[AMOVWF]= {SizeF | LeftRead | RightWrite | Conv},
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[AMOVDF]= {SizeF | LeftRead | RightWrite | Conv},
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[AMOVDW]= {SizeL | LeftRead | RightWrite | Conv},
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[AMOVFD]= {SizeD | LeftRead | RightWrite | Conv},
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[AMOVFW]= {SizeL | LeftRead | RightWrite | Conv},
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// Moves.
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[AMOVB]= {SizeB | LeftRead | RightWrite | Move},
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[AMOVD]= {SizeD | LeftRead | RightWrite | Move},
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[AMOVF]= {SizeF | LeftRead | RightWrite | Move},
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[AMOVH]= {SizeW | LeftRead | RightWrite | Move},
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[AMOVW]= {SizeL | LeftRead | RightWrite | Move},
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// These should be split into the two different conversions instead
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// of overloading the one.
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[AMOVBS]= {SizeB | LeftRead | RightWrite | Conv},
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[AMOVBU]= {SizeB | LeftRead | RightWrite | Conv},
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[AMOVHS]= {SizeW | LeftRead | RightWrite | Conv},
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[AMOVHU]= {SizeW | LeftRead | RightWrite | Conv},
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// Jumps.
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[AB]= {Jump},
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[ABL]= {Call},
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[ABEQ]= {Cjmp},
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[ABNE]= {Cjmp},
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[ABCS]= {Cjmp},
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[ABHS]= {Cjmp},
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[ABCC]= {Cjmp},
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[ABLO]= {Cjmp},
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[ABMI]= {Cjmp},
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[ABPL]= {Cjmp},
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[ABVS]= {Cjmp},
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[ABVC]= {Cjmp},
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[ABHI]= {Cjmp},
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[ABLS]= {Cjmp},
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[ABGE]= {Cjmp},
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[ABLT]= {Cjmp},
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[ABGT]= {Cjmp},
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[ABLE]= {Cjmp},
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[ARET]= {Break},
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};
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void
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proginfo(ProgInfo *info, Prog *p)
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{
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*info = progtable[p->as];
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if(info->flags == 0)
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fatal("unknown instruction %P", p);
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if((info->flags & RegRead) && p->reg == NREG) {
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info->flags &= ~RegRead;
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info->flags |= CanRegRead | RightRead;
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}
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if(((p->scond & C_SCOND) != C_SCOND_NONE) && (info->flags & RightWrite))
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info->flags |= RightRead;
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}
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160
src/cmd/5g/reg.c
160
src/cmd/5g/reg.c
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@ -180,7 +180,8 @@ regopt(Prog *firstp)
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int i, z, nr;
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uint32 vreg;
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Bits bit;
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ProgInfo info, info2;
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if(first == 0) {
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fmtinstall('Q', Qconv);
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}
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@ -243,14 +244,10 @@ regopt(Prog *firstp)
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*/
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nr = 0;
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for(p=firstp; p != P; p = p->link) {
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switch(p->as) {
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case ADATA:
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case AGLOBL:
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case ANAME:
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case ASIGNAME:
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case ATYPE:
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proginfo(&info, p);
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if(info.flags & Skip)
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continue;
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}
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r = rega();
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nr++;
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if(firstr == R) {
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@ -267,10 +264,8 @@ regopt(Prog *firstp)
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r1 = r->p1;
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if(r1 != R) {
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switch(r1->prog->as) {
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case ARET:
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case AB:
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case ARFE:
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proginfo(&info2, r1->prog);
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if(info2.flags & Break) {
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r->p1 = R;
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r1->s1 = R;
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}
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@ -280,140 +275,29 @@ regopt(Prog *firstp)
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if(p->as == ABL && p->to.type == D_EXTERN)
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continue;
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/*
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* left side always read
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*/
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bit = mkvar(r, &p->from);
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for(z=0; z<BITS; z++)
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r->use1.b[z] |= bit.b[z];
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/*
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* middle always read when present
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*/
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if(p->reg != NREG) {
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if(info.flags & LeftRead) {
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bit = mkvar(r, &p->from);
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for(z=0; z<BITS; z++)
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r->use1.b[z] |= bit.b[z];
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}
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if(info.flags & RegRead) {
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if(p->from.type != D_FREG)
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r->use1.b[0] |= RtoB(p->reg);
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else
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r->use1.b[0] |= FtoB(p->reg);
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}
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/*
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* right side depends on opcode
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*/
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bit = mkvar(r, &p->to);
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if(bany(&bit))
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switch(p->as) {
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default:
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yyerror("reg: unknown op: %A", p->as);
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break;
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/*
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* right side read
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*/
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case ATST:
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case ATEQ:
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case ACMP:
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case ACMN:
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case ACMPD:
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case ACMPF:
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rightread:
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for(z=0; z<BITS; z++)
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r->use2.b[z] |= bit.b[z];
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break;
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/*
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* right side read or read+write, depending on middle
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* ADD x, z => z += x
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* ADD x, y, z => z = x + y
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*/
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case AADD:
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case AAND:
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case AEOR:
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case ASUB:
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case ARSB:
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case AADC:
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case ASBC:
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case ARSC:
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case AORR:
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case ABIC:
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case ASLL:
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case ASRL:
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case ASRA:
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case AMUL:
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case AMULU:
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case ADIV:
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case AMOD:
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case AMODU:
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case ADIVU:
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if(p->reg != NREG)
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goto rightread;
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// fall through
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/*
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* right side read+write
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*/
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case AADDF:
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case AADDD:
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case ASUBF:
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case ASUBD:
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case AMULF:
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case AMULD:
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case ADIVF:
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case ADIVD:
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case AMULA:
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case AMULAL:
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case AMULALU:
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for(z=0; z<BITS; z++) {
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r->use2.b[z] |= bit.b[z];
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r->set.b[z] |= bit.b[z];
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}
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break;
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/*
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* right side write
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*/
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case ANOP:
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case AMOVB:
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case AMOVBS:
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case AMOVBU:
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case AMOVD:
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case AMOVDF:
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case AMOVDW:
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case AMOVF:
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case AMOVFW:
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case AMOVH:
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case AMOVHS:
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case AMOVHU:
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case AMOVW:
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case AMOVWD:
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case AMOVWF:
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case AMVN:
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case AMULL:
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case AMULLU:
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if((p->scond & C_SCOND) != C_SCOND_NONE)
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if(info.flags & (RightAddr | RightRead | RightWrite)) {
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bit = mkvar(r, &p->to);
|
||||
if(info.flags & RightAddr)
|
||||
setaddrs(bit);
|
||||
if(info.flags & RightRead)
|
||||
for(z=0; z<BITS; z++)
|
||||
r->use2.b[z] |= bit.b[z];
|
||||
for(z=0; z<BITS; z++)
|
||||
r->set.b[z] |= bit.b[z];
|
||||
break;
|
||||
|
||||
/*
|
||||
* funny
|
||||
*/
|
||||
case ABL:
|
||||
setaddrs(bit);
|
||||
break;
|
||||
}
|
||||
|
||||
if(p->as == AMOVM) {
|
||||
z = p->to.offset;
|
||||
if(p->from.type == D_CONST)
|
||||
z = p->from.offset;
|
||||
for(i=0; z; i++) {
|
||||
if(z&1)
|
||||
regbits |= RtoB(i);
|
||||
z >>= 1;
|
||||
}
|
||||
if(info.flags & RightWrite)
|
||||
for(z=0; z<BITS; z++)
|
||||
r->set.b[z] |= bit.b[z];
|
||||
}
|
||||
}
|
||||
if(firstr == R)
|
||||
|
|
|
|||
Loading…
Reference in New Issue