mirror of https://github.com/golang/go.git
cmd/compile: add MIPS64 optimizations, SSA on by default
Add the following optimizations: - fold constants - fold address into load/store - simplify extensions and conditional branches - remove nil checks Turn on SSA on MIPS64 by default, and toggle the tests. Fixes #16359. Change-Id: I7f1e38c2509e22e42cd024e712990ebbe47176bd Reviewed-on: https://go-review.googlesource.com/27870 Run-TryBot: Cherry Zhang <cherryyz@google.com> Reviewed-by: David Chase <drchase@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
This commit is contained in:
Cherry Zhang
parent
9f7ea61674
commit
7f27f1dfdd
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@ -40,7 +40,7 @@ func shouldssa(fn *Node) bool {
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if os.Getenv("SSATEST") == "" {
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if os.Getenv("SSATEST") == "" {
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return false
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return false
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}
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}
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case "amd64", "amd64p32", "arm", "386", "arm64", "ppc64le":
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case "amd64", "amd64p32", "arm", "386", "arm64", "ppc64le", "mips64", "mips64le":
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// Generally available.
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// Generally available.
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}
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}
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if !ssaEnabled {
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if !ssaEnabled {
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@ -421,7 +421,32 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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ssa.OpMIPS64MOVHUreg,
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ssa.OpMIPS64MOVHUreg,
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ssa.OpMIPS64MOVWreg,
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ssa.OpMIPS64MOVWreg,
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ssa.OpMIPS64MOVWUreg:
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ssa.OpMIPS64MOVWUreg:
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// TODO: remove extension if after proper load
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a := v.Args[0]
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for a.Op == ssa.OpCopy || a.Op == ssa.OpMIPS64MOVVreg {
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a = a.Args[0]
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}
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if a.Op == ssa.OpLoadReg {
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t := a.Type
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switch {
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case v.Op == ssa.OpMIPS64MOVBreg && t.Size() == 1 && t.IsSigned(),
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v.Op == ssa.OpMIPS64MOVBUreg && t.Size() == 1 && !t.IsSigned(),
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v.Op == ssa.OpMIPS64MOVHreg && t.Size() == 2 && t.IsSigned(),
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v.Op == ssa.OpMIPS64MOVHUreg && t.Size() == 2 && !t.IsSigned(),
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v.Op == ssa.OpMIPS64MOVWreg && t.Size() == 4 && t.IsSigned(),
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v.Op == ssa.OpMIPS64MOVWUreg && t.Size() == 4 && !t.IsSigned():
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// arg is a proper-typed load, already zero/sign-extended, don't extend again
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if gc.SSARegNum(v) == gc.SSARegNum(v.Args[0]) {
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return
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}
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p := gc.Prog(mips.AMOVV)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = gc.SSARegNum(v.Args[0])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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return
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default:
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}
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}
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fallthrough
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fallthrough
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case ssa.OpMIPS64MOVWF,
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case ssa.OpMIPS64MOVWF,
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ssa.OpMIPS64MOVWD,
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ssa.OpMIPS64MOVWD,
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@ -613,7 +638,64 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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gc.Maxarg = v.AuxInt
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gc.Maxarg = v.AuxInt
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}
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}
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case ssa.OpMIPS64LoweredNilCheck:
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case ssa.OpMIPS64LoweredNilCheck:
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// TODO: optimization
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// Optimization - if the subsequent block has a load or store
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// at the same address, we don't need to issue this instruction.
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mem := v.Args[1]
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for _, w := range v.Block.Succs[0].Block().Values {
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if w.Op == ssa.OpPhi {
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if w.Type.IsMemory() {
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mem = w
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}
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continue
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}
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if len(w.Args) == 0 || !w.Args[len(w.Args)-1].Type.IsMemory() {
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// w doesn't use a store - can't be a memory op.
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continue
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}
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if w.Args[len(w.Args)-1] != mem {
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v.Fatalf("wrong store after nilcheck v=%s w=%s", v, w)
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}
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switch w.Op {
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case ssa.OpMIPS64MOVBload, ssa.OpMIPS64MOVBUload, ssa.OpMIPS64MOVHload, ssa.OpMIPS64MOVHUload,
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ssa.OpMIPS64MOVWload, ssa.OpMIPS64MOVWUload, ssa.OpMIPS64MOVVload,
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ssa.OpMIPS64MOVFload, ssa.OpMIPS64MOVDload,
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ssa.OpMIPS64MOVBstore, ssa.OpMIPS64MOVHstore, ssa.OpMIPS64MOVWstore, ssa.OpMIPS64MOVVstore,
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ssa.OpMIPS64MOVFstore, ssa.OpMIPS64MOVDstore:
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// arg0 is ptr, auxint is offset
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if w.Args[0] == v.Args[0] && w.Aux == nil && w.AuxInt >= 0 && w.AuxInt < minZeroPage {
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if gc.Debug_checknil != 0 && int(v.Line) > 1 {
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gc.Warnl(v.Line, "removed nil check")
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}
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return
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}
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case ssa.OpMIPS64DUFFZERO, ssa.OpMIPS64LoweredZero:
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// arg0 is ptr
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if w.Args[0] == v.Args[0] {
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if gc.Debug_checknil != 0 && int(v.Line) > 1 {
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gc.Warnl(v.Line, "removed nil check")
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}
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return
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}
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case ssa.OpMIPS64LoweredMove:
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// arg0 is dst ptr, arg1 is src ptr
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if w.Args[0] == v.Args[0] || w.Args[1] == v.Args[0] {
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if gc.Debug_checknil != 0 && int(v.Line) > 1 {
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gc.Warnl(v.Line, "removed nil check")
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}
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return
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}
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default:
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}
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if w.Type.IsMemory() {
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if w.Op == ssa.OpVarDef || w.Op == ssa.OpVarKill || w.Op == ssa.OpVarLive {
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// these ops are OK
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mem = w
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continue
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}
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// We can't delay the nil check past the next store.
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break
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}
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}
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// Issue a load which will fault if arg is nil.
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// Issue a load which will fault if arg is nil.
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p := gc.Prog(mips.AMOVB)
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p := gc.Prog(mips.AMOVB)
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p.From.Type = obj.TYPE_MEM
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p.From.Type = obj.TYPE_MEM
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@ -436,3 +436,271 @@
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// Absorb boolean tests into block
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// Absorb boolean tests into block
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(NE (FPFlagTrue cmp) yes no) -> (FPT cmp yes no)
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(NE (FPFlagTrue cmp) yes no) -> (FPT cmp yes no)
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(NE (FPFlagFalse cmp) yes no) -> (FPF cmp yes no)
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(NE (FPFlagFalse cmp) yes no) -> (FPF cmp yes no)
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(EQ (FPFlagTrue cmp) yes no) -> (FPF cmp yes no)
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(EQ (FPFlagFalse cmp) yes no) -> (FPT cmp yes no)
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(NE (XORconst [1] cmp:(SGT _ _)) yes no) -> (EQ cmp yes no)
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(NE (XORconst [1] cmp:(SGTU _ _)) yes no) -> (EQ cmp yes no)
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(NE (XORconst [1] cmp:(SGTconst _)) yes no) -> (EQ cmp yes no)
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(NE (XORconst [1] cmp:(SGTUconst _)) yes no) -> (EQ cmp yes no)
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(EQ (XORconst [1] cmp:(SGT _ _)) yes no) -> (NE cmp yes no)
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(EQ (XORconst [1] cmp:(SGTU _ _)) yes no) -> (NE cmp yes no)
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(EQ (XORconst [1] cmp:(SGTconst _)) yes no) -> (NE cmp yes no)
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(EQ (XORconst [1] cmp:(SGTUconst _)) yes no) -> (NE cmp yes no)
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(NE (SGTUconst [1] x) yes no) -> (EQ x yes no)
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(EQ (SGTUconst [1] x) yes no) -> (NE x yes no)
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(NE (SGTU x (MOVVconst [0])) yes no) -> (NE x yes no)
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(EQ (SGTU x (MOVVconst [0])) yes no) -> (EQ x yes no)
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(NE (SGTconst [0] x) yes no) -> (LTZ x yes no)
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(EQ (SGTconst [0] x) yes no) -> (GEZ x yes no)
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(NE (SGT x (MOVVconst [0])) yes no) -> (GTZ x yes no)
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(EQ (SGT x (MOVVconst [0])) yes no) -> (LEZ x yes no)
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// fold offset into address
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(ADDVconst [off1] (MOVVaddr [off2] {sym} ptr)) -> (MOVVaddr [off1+off2] {sym} ptr)
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// fold address into load/store
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(MOVBload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBload [off1+off2] {sym} ptr mem)
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(MOVBUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBUload [off1+off2] {sym} ptr mem)
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(MOVHload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHload [off1+off2] {sym} ptr mem)
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(MOVHUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHUload [off1+off2] {sym} ptr mem)
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(MOVWload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWload [off1+off2] {sym} ptr mem)
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(MOVWUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWUload [off1+off2] {sym} ptr mem)
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(MOVVload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVVload [off1+off2] {sym} ptr mem)
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(MOVFload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVFload [off1+off2] {sym} ptr mem)
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(MOVDload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVDload [off1+off2] {sym} ptr mem)
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(MOVBstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} ptr val mem)
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(MOVHstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVHstore [off1+off2] {sym} ptr val mem)
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(MOVWstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} ptr val mem)
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(MOVVstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVVstore [off1+off2] {sym} ptr val mem)
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(MOVFstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVFstore [off1+off2] {sym} ptr val mem)
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(MOVDstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVDstore [off1+off2] {sym} ptr val mem)
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(MOVBstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBstorezero [off1+off2] {sym} ptr mem)
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(MOVHstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHstorezero [off1+off2] {sym} ptr mem)
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(MOVWstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWstorezero [off1+off2] {sym} ptr mem)
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(MOVVstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVVstorezero [off1+off2] {sym} ptr mem)
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(MOVBload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVBUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVHload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVHUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVWload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVWUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVVload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVVload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVFload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVFload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVDload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVBstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
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(MOVHstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
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(MOVWstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
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(MOVVstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVVstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
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(MOVFstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVFstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
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(MOVDstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
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(MOVBstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVHstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVWstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVVstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
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(MOVVstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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// store zero
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(MOVBstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVBstorezero [off] {sym} ptr mem)
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(MOVHstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVHstorezero [off] {sym} ptr mem)
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(MOVWstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVWstorezero [off] {sym} ptr mem)
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(MOVVstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVVstorezero [off] {sym} ptr mem)
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// don't extend after proper load
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(MOVBreg x:(MOVBload _ _)) -> (MOVVreg x)
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(MOVBUreg x:(MOVBUload _ _)) -> (MOVVreg x)
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(MOVHreg x:(MOVBload _ _)) -> (MOVVreg x)
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(MOVHreg x:(MOVBUload _ _)) -> (MOVVreg x)
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(MOVHreg x:(MOVHload _ _)) -> (MOVVreg x)
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(MOVHUreg x:(MOVBUload _ _)) -> (MOVVreg x)
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(MOVHUreg x:(MOVHUload _ _)) -> (MOVVreg x)
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(MOVWreg x:(MOVBload _ _)) -> (MOVVreg x)
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(MOVWreg x:(MOVBUload _ _)) -> (MOVVreg x)
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(MOVWreg x:(MOVHload _ _)) -> (MOVVreg x)
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(MOVWreg x:(MOVHUload _ _)) -> (MOVVreg x)
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(MOVWreg x:(MOVWload _ _)) -> (MOVVreg x)
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(MOVWUreg x:(MOVBUload _ _)) -> (MOVVreg x)
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(MOVWUreg x:(MOVHUload _ _)) -> (MOVVreg x)
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(MOVWUreg x:(MOVWUload _ _)) -> (MOVVreg x)
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// fold double extensions
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(MOVBreg x:(MOVBreg _)) -> (MOVVreg x)
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(MOVBUreg x:(MOVBUreg _)) -> (MOVVreg x)
|
||||||
|
(MOVHreg x:(MOVBreg _)) -> (MOVVreg x)
|
||||||
|
(MOVHreg x:(MOVBUreg _)) -> (MOVVreg x)
|
||||||
|
(MOVHreg x:(MOVHreg _)) -> (MOVVreg x)
|
||||||
|
(MOVHUreg x:(MOVBUreg _)) -> (MOVVreg x)
|
||||||
|
(MOVHUreg x:(MOVHUreg _)) -> (MOVVreg x)
|
||||||
|
(MOVWreg x:(MOVBreg _)) -> (MOVVreg x)
|
||||||
|
(MOVWreg x:(MOVBUreg _)) -> (MOVVreg x)
|
||||||
|
(MOVWreg x:(MOVHreg _)) -> (MOVVreg x)
|
||||||
|
(MOVWreg x:(MOVHreg _)) -> (MOVVreg x)
|
||||||
|
(MOVWreg x:(MOVWreg _)) -> (MOVVreg x)
|
||||||
|
(MOVWUreg x:(MOVBUreg _)) -> (MOVVreg x)
|
||||||
|
(MOVWUreg x:(MOVHUreg _)) -> (MOVVreg x)
|
||||||
|
(MOVWUreg x:(MOVWUreg _)) -> (MOVVreg x)
|
||||||
|
|
||||||
|
// don't extend before store
|
||||||
|
(MOVBstore [off] {sym} ptr (MOVBreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
|
||||||
|
(MOVBstore [off] {sym} ptr (MOVBUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
|
||||||
|
(MOVBstore [off] {sym} ptr (MOVHreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
|
||||||
|
(MOVBstore [off] {sym} ptr (MOVHUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
|
||||||
|
(MOVBstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
|
||||||
|
(MOVBstore [off] {sym} ptr (MOVWUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
|
||||||
|
(MOVHstore [off] {sym} ptr (MOVHreg x) mem) -> (MOVHstore [off] {sym} ptr x mem)
|
||||||
|
(MOVHstore [off] {sym} ptr (MOVHUreg x) mem) -> (MOVHstore [off] {sym} ptr x mem)
|
||||||
|
(MOVHstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVHstore [off] {sym} ptr x mem)
|
||||||
|
(MOVHstore [off] {sym} ptr (MOVWUreg x) mem) -> (MOVHstore [off] {sym} ptr x mem)
|
||||||
|
(MOVWstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVWstore [off] {sym} ptr x mem)
|
||||||
|
(MOVWstore [off] {sym} ptr (MOVWUreg x) mem) -> (MOVWstore [off] {sym} ptr x mem)
|
||||||
|
|
||||||
|
// if a register move has only 1 use, just use the same register without emitting instruction
|
||||||
|
// MOVVnop doesn't emit instruction, only for ensuring the type.
|
||||||
|
(MOVVreg x) && x.Uses == 1 -> (MOVVnop x)
|
||||||
|
|
||||||
|
// fold constant into arithmatic ops
|
||||||
|
(ADDV (MOVVconst [c]) x) && is32Bit(c) -> (ADDVconst [c] x)
|
||||||
|
(ADDV x (MOVVconst [c])) && is32Bit(c) -> (ADDVconst [c] x)
|
||||||
|
(SUBV x (MOVVconst [c])) && is32Bit(c) -> (SUBVconst [c] x)
|
||||||
|
(AND (MOVVconst [c]) x) && is32Bit(c) -> (ANDconst [c] x)
|
||||||
|
(AND x (MOVVconst [c])) && is32Bit(c) -> (ANDconst [c] x)
|
||||||
|
(OR (MOVVconst [c]) x) && is32Bit(c) -> (ORconst [c] x)
|
||||||
|
(OR x (MOVVconst [c])) && is32Bit(c) -> (ORconst [c] x)
|
||||||
|
(XOR (MOVVconst [c]) x) && is32Bit(c) -> (XORconst [c] x)
|
||||||
|
(XOR x (MOVVconst [c])) && is32Bit(c) -> (XORconst [c] x)
|
||||||
|
(NOR (MOVVconst [c]) x) && is32Bit(c) -> (NORconst [c] x)
|
||||||
|
(NOR x (MOVVconst [c])) && is32Bit(c) -> (NORconst [c] x)
|
||||||
|
|
||||||
|
(SLLV _ (MOVVconst [c])) && uint64(c)>=64 -> (MOVVconst [0])
|
||||||
|
(SRLV _ (MOVVconst [c])) && uint64(c)>=64 -> (MOVVconst [0])
|
||||||
|
(SRAV x (MOVVconst [c])) && uint64(c)>=64 -> (SRAVconst x [63])
|
||||||
|
(SLLV x (MOVVconst [c])) -> (SLLVconst x [c])
|
||||||
|
(SRLV x (MOVVconst [c])) -> (SRLVconst x [c])
|
||||||
|
(SRAV x (MOVVconst [c])) -> (SRAVconst x [c])
|
||||||
|
|
||||||
|
(SGT (MOVVconst [c]) x) && is32Bit(c) -> (SGTconst [c] x)
|
||||||
|
(SGTU (MOVVconst [c]) x) && is32Bit(c) -> (SGTUconst [c] x)
|
||||||
|
|
||||||
|
// mul by constant
|
||||||
|
(Select1 (MULVU x (MOVVconst [-1]))) -> (NEGV x)
|
||||||
|
(Select1 (MULVU _ (MOVVconst [0]))) -> (MOVVconst [0])
|
||||||
|
(Select1 (MULVU x (MOVVconst [1]))) -> x
|
||||||
|
(Select1 (MULVU x (MOVVconst [c]))) && isPowerOfTwo(c) -> (SLLVconst [log2(c)] x)
|
||||||
|
|
||||||
|
(Select1 (MULVU (MOVVconst [-1]) x)) -> (NEGV x)
|
||||||
|
(Select1 (MULVU (MOVVconst [0]) _)) -> (MOVVconst [0])
|
||||||
|
(Select1 (MULVU (MOVVconst [1]) x)) -> x
|
||||||
|
(Select1 (MULVU (MOVVconst [c]) x)) && isPowerOfTwo(c) -> (SLLVconst [log2(c)] x)
|
||||||
|
|
||||||
|
// div by constant
|
||||||
|
(Select1 (DIVVU x (MOVVconst [1]))) -> x
|
||||||
|
(Select1 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo(c) -> (SRLVconst [log2(c)] x)
|
||||||
|
(Select0 (DIVVU _ (MOVVconst [1]))) -> (MOVVconst [0]) // mod
|
||||||
|
(Select0 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo(c) -> (ANDconst [c-1] x) // mod
|
||||||
|
|
||||||
|
// generic simplifications
|
||||||
|
(ADDV x (NEGV y)) -> (SUBV x y)
|
||||||
|
(ADDV (NEGV y) x) -> (SUBV x y)
|
||||||
|
(SUBV x x) -> (MOVVconst [0])
|
||||||
|
(SUBV (MOVVconst [0]) x) -> (NEGV x)
|
||||||
|
(AND x x) -> x
|
||||||
|
(OR x x) -> x
|
||||||
|
(XOR x x) -> (MOVVconst [0])
|
||||||
|
|
||||||
|
// remove redundant *const ops
|
||||||
|
(ADDVconst [0] x) -> x
|
||||||
|
(SUBVconst [0] x) -> x
|
||||||
|
(ANDconst [0] _) -> (MOVVconst [0])
|
||||||
|
(ANDconst [-1] x) -> x
|
||||||
|
(ORconst [0] x) -> x
|
||||||
|
(ORconst [-1] _) -> (MOVVconst [-1])
|
||||||
|
(XORconst [0] x) -> x
|
||||||
|
(XORconst [-1] x) -> (NORconst [0] x)
|
||||||
|
|
||||||
|
// generic constant folding
|
||||||
|
(ADDVconst [c] (MOVVconst [d])) -> (MOVVconst [c+d])
|
||||||
|
(ADDVconst [c] (ADDVconst [d] x)) && is32Bit(c+d) -> (ADDVconst [c+d] x)
|
||||||
|
(ADDVconst [c] (SUBVconst [d] x)) && is32Bit(c-d) -> (ADDVconst [c-d] x)
|
||||||
|
(SUBVconst [c] (MOVVconst [d])) -> (MOVVconst [d-c])
|
||||||
|
(SUBVconst [c] (SUBVconst [d] x)) && is32Bit(-c-d) -> (ADDVconst [-c-d] x)
|
||||||
|
(SUBVconst [c] (ADDVconst [d] x)) && is32Bit(-c+d) -> (ADDVconst [-c+d] x)
|
||||||
|
(SLLVconst [c] (MOVVconst [d])) -> (MOVVconst [int64(d)<<uint64(c)])
|
||||||
|
(SRLVconst [c] (MOVVconst [d])) -> (MOVVconst [int64(uint64(d)>>uint64(c))])
|
||||||
|
(SRAVconst [c] (MOVVconst [d])) -> (MOVVconst [int64(d)>>uint64(c)])
|
||||||
|
(Select1 (MULVU (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [c*d])
|
||||||
|
(Select1 (DIVV (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(c)/int64(d)])
|
||||||
|
(Select1 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(uint64(c)/uint64(d))])
|
||||||
|
(Select0 (DIVV (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(c)%int64(d)]) // mod
|
||||||
|
(Select0 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(uint64(c)%uint64(d))]) // mod
|
||||||
|
(ANDconst [c] (MOVVconst [d])) -> (MOVVconst [c&d])
|
||||||
|
(ANDconst [c] (ANDconst [d] x)) -> (ANDconst [c&d] x)
|
||||||
|
(ORconst [c] (MOVVconst [d])) -> (MOVVconst [c|d])
|
||||||
|
(ORconst [c] (ORconst [d] x)) && is32Bit(c|d) -> (ORconst [c|d] x)
|
||||||
|
(XORconst [c] (MOVVconst [d])) -> (MOVVconst [c^d])
|
||||||
|
(XORconst [c] (XORconst [d] x)) && is32Bit(c^d) -> (XORconst [c^d] x)
|
||||||
|
(NORconst [c] (MOVVconst [d])) -> (MOVVconst [^(c|d)])
|
||||||
|
(NEGV (MOVVconst [c])) -> (MOVVconst [-c])
|
||||||
|
(MOVBreg (MOVVconst [c])) -> (MOVVconst [int64(int8(c))])
|
||||||
|
(MOVBUreg (MOVVconst [c])) -> (MOVVconst [int64(uint8(c))])
|
||||||
|
(MOVHreg (MOVVconst [c])) -> (MOVVconst [int64(int16(c))])
|
||||||
|
(MOVHUreg (MOVVconst [c])) -> (MOVVconst [int64(uint16(c))])
|
||||||
|
(MOVWreg (MOVVconst [c])) -> (MOVVconst [int64(int32(c))])
|
||||||
|
(MOVWUreg (MOVVconst [c])) -> (MOVVconst [int64(uint32(c))])
|
||||||
|
(MOVVreg (MOVVconst [c])) -> (MOVVconst [c])
|
||||||
|
|
||||||
|
// constant comparisons
|
||||||
|
(SGTconst [c] (MOVVconst [d])) && int64(c)>int64(d) -> (MOVVconst [1])
|
||||||
|
(SGTconst [c] (MOVVconst [d])) && int64(c)<=int64(d) -> (MOVVconst [0])
|
||||||
|
(SGTUconst [c] (MOVVconst [d])) && uint64(c)>uint64(d) -> (MOVVconst [1])
|
||||||
|
(SGTUconst [c] (MOVVconst [d])) && uint64(c)<=uint64(d) -> (MOVVconst [0])
|
||||||
|
|
||||||
|
// other known comparisons
|
||||||
|
(SGTconst [c] (MOVBreg _)) && 0x7f < int64(c) -> (MOVVconst [1])
|
||||||
|
(SGTconst [c] (MOVBreg _)) && int64(c) <= -0x80 -> (MOVVconst [0])
|
||||||
|
(SGTconst [c] (MOVBUreg _)) && 0xff < int64(c) -> (MOVVconst [1])
|
||||||
|
(SGTconst [c] (MOVBUreg _)) && int64(c) < 0 -> (MOVVconst [0])
|
||||||
|
(SGTUconst [c] (MOVBUreg _)) && 0xff < uint64(c) -> (MOVVconst [1])
|
||||||
|
(SGTconst [c] (MOVHreg _)) && 0x7fff < int64(c) -> (MOVVconst [1])
|
||||||
|
(SGTconst [c] (MOVHreg _)) && int64(c) <= -0x8000 -> (MOVVconst [0])
|
||||||
|
(SGTconst [c] (MOVHUreg _)) && 0xffff < int64(c) -> (MOVVconst [1])
|
||||||
|
(SGTconst [c] (MOVHUreg _)) && int64(c) < 0 -> (MOVVconst [0])
|
||||||
|
(SGTUconst [c] (MOVHUreg _)) && 0xffff < uint64(c) -> (MOVVconst [1])
|
||||||
|
(SGTconst [c] (MOVWUreg _)) && int64(c) < 0 -> (MOVVconst [0])
|
||||||
|
(SGTconst [c] (ANDconst [m] _)) && 0 <= m && m < c -> (MOVVconst [1])
|
||||||
|
(SGTUconst [c] (ANDconst [m] _)) && uint64(m) < uint64(c) -> (MOVVconst [1])
|
||||||
|
(SGTconst [c] (SRLVconst _ [d])) && 0 <= c && 0 < d && d <= 63 && 1<<uint64(64-d) <= c -> (MOVVconst [1])
|
||||||
|
(SGTUconst [c] (SRLVconst _ [d])) && 0 < d && d <= 63 && 1<<uint64(64-d) <= uint64(c) -> (MOVVconst [1])
|
||||||
|
|
||||||
|
// absorb constants into branches
|
||||||
|
(EQ (MOVVconst [0]) yes no) -> (First nil yes no)
|
||||||
|
(EQ (MOVVconst [c]) yes no) && c != 0 -> (First nil no yes)
|
||||||
|
(NE (MOVVconst [0]) yes no) -> (First nil no yes)
|
||||||
|
(NE (MOVVconst [c]) yes no) && c != 0 -> (First nil yes no)
|
||||||
|
(LTZ (MOVVconst [c]) yes no) && c < 0 -> (First nil yes no)
|
||||||
|
(LTZ (MOVVconst [c]) yes no) && c >= 0 -> (First nil no yes)
|
||||||
|
(LEZ (MOVVconst [c]) yes no) && c <= 0 -> (First nil yes no)
|
||||||
|
(LEZ (MOVVconst [c]) yes no) && c > 0 -> (First nil no yes)
|
||||||
|
(GTZ (MOVVconst [c]) yes no) && c > 0 -> (First nil yes no)
|
||||||
|
(GTZ (MOVVconst [c]) yes no) && c <= 0 -> (First nil no yes)
|
||||||
|
(GEZ (MOVVconst [c]) yes no) && c >= 0 -> (First nil yes no)
|
||||||
|
(GEZ (MOVVconst [c]) yes no) && c < 0 -> (First nil no yes)
|
||||||
|
|
|
||||||
|
|
@ -201,9 +201,9 @@ func init() {
|
||||||
|
|
||||||
// comparisons
|
// comparisons
|
||||||
{name: "SGT", argLength: 2, reg: gp21, asm: "SGT", typ: "Bool"}, // 1 if arg0 > arg1 (signed), 0 otherwise
|
{name: "SGT", argLength: 2, reg: gp21, asm: "SGT", typ: "Bool"}, // 1 if arg0 > arg1 (signed), 0 otherwise
|
||||||
{name: "SGTconst", argLength: 2, reg: gp21, asm: "SGT", aux: "Int64", typ: "Bool"}, // 1 if arg0 > auxInt (signed), 0 otherwise
|
{name: "SGTconst", argLength: 1, reg: gp11, asm: "SGT", aux: "Int64", typ: "Bool"}, // 1 if auxInt > arg0 (signed), 0 otherwise
|
||||||
{name: "SGTU", argLength: 2, reg: gp21, asm: "SGTU", typ: "Bool"}, // 1 if arg0 > arg1 (unsigned), 0 otherwise
|
{name: "SGTU", argLength: 2, reg: gp21, asm: "SGTU", typ: "Bool"}, // 1 if arg0 > arg1 (unsigned), 0 otherwise
|
||||||
{name: "SGTUconst", argLength: 2, reg: gp21, asm: "SGTU", aux: "Int64", typ: "Bool"}, // 1 if arg0 > auxInt (unsigned), 0 otherwise
|
{name: "SGTUconst", argLength: 1, reg: gp11, asm: "SGTU", aux: "Int64", typ: "Bool"}, // 1 if auxInt > arg0 (unsigned), 0 otherwise
|
||||||
|
|
||||||
{name: "CMPEQF", argLength: 2, reg: fp2flags, asm: "CMPEQF", typ: "Flags"}, // flags=true if arg0 = arg1, float32
|
{name: "CMPEQF", argLength: 2, reg: fp2flags, asm: "CMPEQF", typ: "Flags"}, // flags=true if arg0 = arg1, float32
|
||||||
{name: "CMPEQD", argLength: 2, reg: fp2flags, asm: "CMPEQD", typ: "Flags"}, // flags=true if arg0 = arg1, float64
|
{name: "CMPEQD", argLength: 2, reg: fp2flags, asm: "CMPEQD", typ: "Flags"}, // flags=true if arg0 = arg1, float64
|
||||||
|
|
|
||||||
|
|
@ -12421,12 +12421,11 @@ var opcodeTable = [...]opInfo{
|
||||||
{
|
{
|
||||||
name: "SGTconst",
|
name: "SGTconst",
|
||||||
auxType: auxInt64,
|
auxType: auxInt64,
|
||||||
argLen: 2,
|
argLen: 1,
|
||||||
asm: mips.ASGT,
|
asm: mips.ASGT,
|
||||||
reg: regInfo{
|
reg: regInfo{
|
||||||
inputs: []inputInfo{
|
inputs: []inputInfo{
|
||||||
{0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g
|
{0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g
|
||||||
{1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g
|
|
||||||
},
|
},
|
||||||
outputs: []outputInfo{
|
outputs: []outputInfo{
|
||||||
{0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25
|
{0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25
|
||||||
|
|
@ -12450,12 +12449,11 @@ var opcodeTable = [...]opInfo{
|
||||||
{
|
{
|
||||||
name: "SGTUconst",
|
name: "SGTUconst",
|
||||||
auxType: auxInt64,
|
auxType: auxInt64,
|
||||||
argLen: 2,
|
argLen: 1,
|
||||||
asm: mips.ASGTU,
|
asm: mips.ASGTU,
|
||||||
reg: regInfo{
|
reg: regInfo{
|
||||||
inputs: []inputInfo{
|
inputs: []inputInfo{
|
||||||
{0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g
|
{0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g
|
||||||
{1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g
|
|
||||||
},
|
},
|
||||||
outputs: []outputInfo{
|
outputs: []outputInfo{
|
||||||
{0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25
|
{0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,4 +1,4 @@
|
||||||
// +build !amd64,!arm,!amd64p32,!386,!arm64,!ppc64le
|
// +build !amd64,!arm,!amd64p32,!386,!arm64,!ppc64le,!mips64,!mips64le
|
||||||
// errorcheck -0 -l -live -wb=0
|
// errorcheck -0 -l -live -wb=0
|
||||||
|
|
||||||
// Copyright 2014 The Go Authors. All rights reserved.
|
// Copyright 2014 The Go Authors. All rights reserved.
|
||||||
|
|
|
||||||
|
|
@ -1,4 +1,4 @@
|
||||||
// +build amd64 arm amd64p32 386 arm64
|
// +build amd64 arm amd64p32 386 arm64 mips64 mips64le
|
||||||
// errorcheck -0 -l -live -wb=0
|
// errorcheck -0 -l -live -wb=0
|
||||||
|
|
||||||
// Copyright 2014 The Go Authors. All rights reserved.
|
// Copyright 2014 The Go Authors. All rights reserved.
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,5 @@
|
||||||
// errorcheck -0 -d=nil
|
// errorcheck -0 -d=nil
|
||||||
// +build amd64 arm amd64p32 386 arm64
|
// +build amd64 arm amd64p32 386 arm64 mips64 mips64le
|
||||||
|
|
||||||
// Copyright 2013 The Go Authors. All rights reserved.
|
// Copyright 2013 The Go Authors. All rights reserved.
|
||||||
// Use of this source code is governed by a BSD-style
|
// Use of this source code is governed by a BSD-style
|
||||||
|
|
|
||||||
|
|
@ -1,4 +1,4 @@
|
||||||
// +build !amd64,!arm,!amd64p32,!386,!arm64,!ppc64le
|
// +build !amd64,!arm,!amd64p32,!386,!arm64,!ppc64le,!mips64,!mips64le
|
||||||
// errorcheck -0 -d=append,slice
|
// errorcheck -0 -d=append,slice
|
||||||
|
|
||||||
// Copyright 2015 The Go Authors. All rights reserved.
|
// Copyright 2015 The Go Authors. All rights reserved.
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue