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[release-branch.go1.19] cmd/internal/obj/ppc64: fix incorrect base reg causing segv 

This fixes a segv that was reported due to building minio. The
problem occurred because of an incorrect selection of the
base register, which was introduced by CL 306369.

Fixes #59219

Change-Id: Ieb77b2afa8fb4e6f3943df5ce138679f6750d376
Reviewed-on: https://go-review.googlesource.com/c/go/+/479628
Reviewed-by: Cherry Mui <cherryyz@google.com>
Run-TryBot: Lynn Boger <laboger@linux.vnet.ibm.com>
Reviewed-by: Matthew Dempsky <mdempsky@google.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
This commit is contained in:
Lynn Boger 2023-03-27 08:26:59 -05:00 committed by Matthew Dempsky
parent 2adec52b5a
commit 6d9df0a5a6
1 changed files with 9 additions and 4 deletions
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13
src/cmd/internal/obj/ppc64/asm9.go
View File

@ -3136,8 +3136,13 @@ func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) {
if r == 0 {
r = c.getimpliedreg(&p.From, p)
}
o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(v)))
o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
if o.a6 == C_REG {
o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(v)))
o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
} else {
o1 = AOP_IRR(OP_ADDIS, uint32(REGTMP), uint32(r), uint32(high16adjusted(v)))
o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(REGTMP), uint32(v))
}
// Sign extend MOVB if needed
o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
@ -3516,8 +3521,8 @@ func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) {
rel.Type = objabi.R_ADDRPOWER_TOCREL_DS
}
default:
reuseBaseReg := p.As != AFMOVD && p.As != AFMOVS
// Reuse To.Reg as base register if not FP move.
reuseBaseReg := o.a6 == C_REG
// Reuse To.Reg as base register if it is a GPR.
o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst, reuseBaseReg)
}