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cmd/internal/obj/ppc64: fix incorrect base reg causing segv 

This fixes a segv that was reported due to building minio. The
problem occurred because of an incorrect selection of the
base register, which was introduced by CL 306369.

Fixes #59196

Change-Id: Ieb77b2afa8fb4e6f3943df5ce138679f6750d376
Reviewed-on: https://go-review.googlesource.com/c/go/+/478920
Run-TryBot: Lynn Boger <laboger@linux.vnet.ibm.com>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Reviewed-by: Archana Ravindar <aravind5@in.ibm.com>
Reviewed-by: Heschi Kreinick <heschi@google.com>
Auto-Submit: Lynn Boger <laboger@linux.vnet.ibm.com>
Reviewed-by: Paul Murphy <murp@ibm.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
This commit is contained in:
Lynn Boger 2023-03-23 13:19:02 -05:00 committed by Gopher Robot
parent 59d7c69342
commit 2716dfd995
1 changed files with 11 additions and 4 deletions
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11
src/cmd/internal/obj/ppc64/asm9.go
View File

@ -3288,8 +3288,15 @@ func asmout(c *ctxt9, p *obj.Prog, o *Optab, out *[5]uint32) {
o1 |= uint32((v >> 16) & 0x3FFFF)
o2 |= uint32(v & 0xFFFF)
} else {
if o.a6 == C_REG {
// Reuse the base register when loading a GPR (C_REG) to avoid
// using REGTMP (R31) when possible.
o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(v)))
o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
} else {
o1 = AOP_IRR(OP_ADDIS, uint32(REGTMP), uint32(r), uint32(high16adjusted(v)))
o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(REGTMP), uint32(v))
}
}
// Sign extend MOVB if needed
@ -3681,8 +3688,8 @@ func asmout(c *ctxt9, p *obj.Prog, o *Optab, out *[5]uint32) {
rel.Type = objabi.R_ADDRPOWER_TOCREL_DS
}
default:
reuseBaseReg := p.As != AFMOVD && p.As != AFMOVS
// Reuse To.Reg as base register if not FP move.
reuseBaseReg := o.a6 == C_REG
// Reuse To.Reg as base register if it is a GPR.
o1, o2, rel = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst, reuseBaseReg)
}