From 26b5c75530347ef781d762b1d7116ec6e2b64e9c Mon Sep 17 00:00:00 2001 From: Luo Jia Date: Sun, 10 Apr 2022 11:15:49 +0800 Subject: [PATCH] compile: X1 is named as RA under RISC-V, not LR Ref: https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#general-registers This commit does not modify any working code, it only alter one line of comment to enhance readability. --- src/cmd/compile/internal/riscv64/ssa.go | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cmd/compile/internal/riscv64/ssa.go b/src/cmd/compile/internal/riscv64/ssa.go index b6e6dc1a03..0ccd6cfe17 100644 --- a/src/cmd/compile/internal/riscv64/ssa.go +++ b/src/cmd/compile/internal/riscv64/ssa.go @@ -18,7 +18,7 @@ import ( // ssaRegToReg maps ssa register numbers to obj register numbers. var ssaRegToReg = []int16{ riscv.REG_X0, - // X1 (LR): unused + // X1 (ra): unused riscv.REG_X2, riscv.REG_X3, riscv.REG_X4,