mirror of https://github.com/golang/go.git
[release-branch.go1.16] cmd/compile: ensure constant shift amounts are in range for arm
Ensure constant shift amounts are in the range [0-31]. When shift amounts
are out of range, bad things happen. Shift amounts out of range occur
when lowering 64-bit shifts (we take an in-range shift s in [0-63] and
calculate s-32 and 32-s, both of which might be out of [0-31]).
The constant shift operations themselves still work, but their shift
amounts get copied unmolested to operations like ORshiftLL which use only
the low 5 bits. That changes an operation like <<100 which unconditionally
produces 0, to <<4, which doesn't.
Fixes #48478
Change-Id: I87363ef2b4ceaf3b2e316426064626efdfbb8ee3
Reviewed-on: https://go-review.googlesource.com/c/go/+/350969
Trust: Keith Randall <khr@golang.org>
Run-TryBot: Keith Randall <khr@golang.org>
TryBot-Result: Go Bot <gobot@golang.org>
Reviewed-by: Cherry Mui <cherryyz@google.com>
(cherry picked from commit eff27e858b)
Reviewed-on: https://go-review.googlesource.com/c/go/+/351070
Reviewed-by: Austin Clements <austin@google.com>
This commit is contained in:
parent
cfe182c673
commit
1a6281d950
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@ -496,9 +496,9 @@
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(XOR x (MOVWconst [c])) => (XORconst [c] x)
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(BIC x (MOVWconst [c])) => (BICconst [c] x)
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(SLL x (MOVWconst [c])) => (SLLconst x [c&31]) // Note: I don't think we ever generate bad constant shifts (i.e. c>=32)
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(SRL x (MOVWconst [c])) => (SRLconst x [c&31])
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(SRA x (MOVWconst [c])) => (SRAconst x [c&31])
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(SLL x (MOVWconst [c])) && 0 <= c && c < 32 => (SLLconst x [c])
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(SRL x (MOVWconst [c])) && 0 <= c && c < 32 => (SRLconst x [c])
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(SRA x (MOVWconst [c])) && 0 <= c && c < 32 => (SRAconst x [c])
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(CMP x (MOVWconst [c])) => (CMPconst [c] x)
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(CMP (MOVWconst [c]) x) => (InvertFlags (CMPconst [c] x))
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@ -1067,60 +1067,60 @@
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(CMNshiftRL x (MOVWconst [c]) [d]) => (CMNconst x [int32(uint32(c)>>uint64(d))])
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(CMNshiftRA x (MOVWconst [c]) [d]) => (CMNconst x [c>>uint64(d)])
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(ADDshiftLLreg x y (MOVWconst [c])) => (ADDshiftLL x y [c])
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(ADDshiftRLreg x y (MOVWconst [c])) => (ADDshiftRL x y [c])
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(ADDshiftRAreg x y (MOVWconst [c])) => (ADDshiftRA x y [c])
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(ADCshiftLLreg x y (MOVWconst [c]) flags) => (ADCshiftLL x y [c] flags)
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(ADCshiftRLreg x y (MOVWconst [c]) flags) => (ADCshiftRL x y [c] flags)
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(ADCshiftRAreg x y (MOVWconst [c]) flags) => (ADCshiftRA x y [c] flags)
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(ADDSshiftLLreg x y (MOVWconst [c])) => (ADDSshiftLL x y [c])
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(ADDSshiftRLreg x y (MOVWconst [c])) => (ADDSshiftRL x y [c])
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(ADDSshiftRAreg x y (MOVWconst [c])) => (ADDSshiftRA x y [c])
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(SUBshiftLLreg x y (MOVWconst [c])) => (SUBshiftLL x y [c])
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(SUBshiftRLreg x y (MOVWconst [c])) => (SUBshiftRL x y [c])
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(SUBshiftRAreg x y (MOVWconst [c])) => (SUBshiftRA x y [c])
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(SBCshiftLLreg x y (MOVWconst [c]) flags) => (SBCshiftLL x y [c] flags)
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(SBCshiftRLreg x y (MOVWconst [c]) flags) => (SBCshiftRL x y [c] flags)
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(SBCshiftRAreg x y (MOVWconst [c]) flags) => (SBCshiftRA x y [c] flags)
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(SUBSshiftLLreg x y (MOVWconst [c])) => (SUBSshiftLL x y [c])
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(SUBSshiftRLreg x y (MOVWconst [c])) => (SUBSshiftRL x y [c])
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(SUBSshiftRAreg x y (MOVWconst [c])) => (SUBSshiftRA x y [c])
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(RSBshiftLLreg x y (MOVWconst [c])) => (RSBshiftLL x y [c])
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(RSBshiftRLreg x y (MOVWconst [c])) => (RSBshiftRL x y [c])
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(RSBshiftRAreg x y (MOVWconst [c])) => (RSBshiftRA x y [c])
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(RSCshiftLLreg x y (MOVWconst [c]) flags) => (RSCshiftLL x y [c] flags)
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(RSCshiftRLreg x y (MOVWconst [c]) flags) => (RSCshiftRL x y [c] flags)
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(RSCshiftRAreg x y (MOVWconst [c]) flags) => (RSCshiftRA x y [c] flags)
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(RSBSshiftLLreg x y (MOVWconst [c])) => (RSBSshiftLL x y [c])
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(RSBSshiftRLreg x y (MOVWconst [c])) => (RSBSshiftRL x y [c])
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(RSBSshiftRAreg x y (MOVWconst [c])) => (RSBSshiftRA x y [c])
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(ANDshiftLLreg x y (MOVWconst [c])) => (ANDshiftLL x y [c])
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(ANDshiftRLreg x y (MOVWconst [c])) => (ANDshiftRL x y [c])
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(ANDshiftRAreg x y (MOVWconst [c])) => (ANDshiftRA x y [c])
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(ORshiftLLreg x y (MOVWconst [c])) => (ORshiftLL x y [c])
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(ORshiftRLreg x y (MOVWconst [c])) => (ORshiftRL x y [c])
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(ORshiftRAreg x y (MOVWconst [c])) => (ORshiftRA x y [c])
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(XORshiftLLreg x y (MOVWconst [c])) => (XORshiftLL x y [c])
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(XORshiftRLreg x y (MOVWconst [c])) => (XORshiftRL x y [c])
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(XORshiftRAreg x y (MOVWconst [c])) => (XORshiftRA x y [c])
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(BICshiftLLreg x y (MOVWconst [c])) => (BICshiftLL x y [c])
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(BICshiftRLreg x y (MOVWconst [c])) => (BICshiftRL x y [c])
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(BICshiftRAreg x y (MOVWconst [c])) => (BICshiftRA x y [c])
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(MVNshiftLLreg x (MOVWconst [c])) => (MVNshiftLL x [c])
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(MVNshiftRLreg x (MOVWconst [c])) => (MVNshiftRL x [c])
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(MVNshiftRAreg x (MOVWconst [c])) => (MVNshiftRA x [c])
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(CMPshiftLLreg x y (MOVWconst [c])) => (CMPshiftLL x y [c])
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(CMPshiftRLreg x y (MOVWconst [c])) => (CMPshiftRL x y [c])
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(CMPshiftRAreg x y (MOVWconst [c])) => (CMPshiftRA x y [c])
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(TSTshiftLLreg x y (MOVWconst [c])) => (TSTshiftLL x y [c])
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(TSTshiftRLreg x y (MOVWconst [c])) => (TSTshiftRL x y [c])
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(TSTshiftRAreg x y (MOVWconst [c])) => (TSTshiftRA x y [c])
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(TEQshiftLLreg x y (MOVWconst [c])) => (TEQshiftLL x y [c])
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(TEQshiftRLreg x y (MOVWconst [c])) => (TEQshiftRL x y [c])
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(TEQshiftRAreg x y (MOVWconst [c])) => (TEQshiftRA x y [c])
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(CMNshiftLLreg x y (MOVWconst [c])) => (CMNshiftLL x y [c])
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(CMNshiftRLreg x y (MOVWconst [c])) => (CMNshiftRL x y [c])
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(CMNshiftRAreg x y (MOVWconst [c])) => (CMNshiftRA x y [c])
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(ADDshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ADDshiftLL x y [c])
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(ADDshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ADDshiftRL x y [c])
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(ADDshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ADDshiftRA x y [c])
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(ADCshiftLLreg x y (MOVWconst [c]) flags) && 0 <= c && c < 32 => (ADCshiftLL x y [c] flags)
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(ADCshiftRLreg x y (MOVWconst [c]) flags) && 0 <= c && c < 32 => (ADCshiftRL x y [c] flags)
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(ADCshiftRAreg x y (MOVWconst [c]) flags) && 0 <= c && c < 32 => (ADCshiftRA x y [c] flags)
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(ADDSshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ADDSshiftLL x y [c])
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(ADDSshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ADDSshiftRL x y [c])
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(ADDSshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ADDSshiftRA x y [c])
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(SUBshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (SUBshiftLL x y [c])
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(SUBshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (SUBshiftRL x y [c])
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(SUBshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (SUBshiftRA x y [c])
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(SBCshiftLLreg x y (MOVWconst [c]) flags) && 0 <= c && c < 32 => (SBCshiftLL x y [c] flags)
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(SBCshiftRLreg x y (MOVWconst [c]) flags) && 0 <= c && c < 32 => (SBCshiftRL x y [c] flags)
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(SBCshiftRAreg x y (MOVWconst [c]) flags) && 0 <= c && c < 32 => (SBCshiftRA x y [c] flags)
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(SUBSshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (SUBSshiftLL x y [c])
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(SUBSshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (SUBSshiftRL x y [c])
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(SUBSshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (SUBSshiftRA x y [c])
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(RSBshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (RSBshiftLL x y [c])
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(RSBshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (RSBshiftRL x y [c])
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(RSBshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (RSBshiftRA x y [c])
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(RSCshiftLLreg x y (MOVWconst [c]) flags) && 0 <= c && c < 32 => (RSCshiftLL x y [c] flags)
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(RSCshiftRLreg x y (MOVWconst [c]) flags) && 0 <= c && c < 32 => (RSCshiftRL x y [c] flags)
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(RSCshiftRAreg x y (MOVWconst [c]) flags) && 0 <= c && c < 32 => (RSCshiftRA x y [c] flags)
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(RSBSshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (RSBSshiftLL x y [c])
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(RSBSshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (RSBSshiftRL x y [c])
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(RSBSshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (RSBSshiftRA x y [c])
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(ANDshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ANDshiftLL x y [c])
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(ANDshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ANDshiftRL x y [c])
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(ANDshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ANDshiftRA x y [c])
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(ORshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ORshiftLL x y [c])
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(ORshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ORshiftRL x y [c])
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(ORshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ORshiftRA x y [c])
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(XORshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (XORshiftLL x y [c])
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(XORshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (XORshiftRL x y [c])
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(XORshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (XORshiftRA x y [c])
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(BICshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (BICshiftLL x y [c])
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(BICshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (BICshiftRL x y [c])
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(BICshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (BICshiftRA x y [c])
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(MVNshiftLLreg x (MOVWconst [c])) && 0 <= c && c < 32 => (MVNshiftLL x [c])
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(MVNshiftRLreg x (MOVWconst [c])) && 0 <= c && c < 32 => (MVNshiftRL x [c])
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(MVNshiftRAreg x (MOVWconst [c])) && 0 <= c && c < 32 => (MVNshiftRA x [c])
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(CMPshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (CMPshiftLL x y [c])
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(CMPshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (CMPshiftRL x y [c])
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(CMPshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (CMPshiftRA x y [c])
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(TSTshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (TSTshiftLL x y [c])
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(TSTshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (TSTshiftRL x y [c])
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(TSTshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (TSTshiftRA x y [c])
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(TEQshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (TEQshiftLL x y [c])
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(TEQshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (TEQshiftRL x y [c])
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(TEQshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (TEQshiftRA x y [c])
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(CMNshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (CMNshiftLL x y [c])
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(CMNshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (CMNshiftRL x y [c])
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(CMNshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (CMNshiftRA x y [c])
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// Generate rotates
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(ADDshiftLL [c] (SRLconst x [32-c]) x) => (SRRconst [32-c] x)
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@ -226,14 +226,15 @@ func init() {
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// shifts
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{name: "SLL", argLength: 2, reg: gp21, asm: "SLL"}, // arg0 << arg1, shift amount is mod 256
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{name: "SLLconst", argLength: 1, reg: gp11, asm: "SLL", aux: "Int32"}, // arg0 << auxInt
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{name: "SLLconst", argLength: 1, reg: gp11, asm: "SLL", aux: "Int32"}, // arg0 << auxInt, 0 <= auxInt < 32
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{name: "SRL", argLength: 2, reg: gp21, asm: "SRL"}, // arg0 >> arg1, unsigned, shift amount is mod 256
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{name: "SRLconst", argLength: 1, reg: gp11, asm: "SRL", aux: "Int32"}, // arg0 >> auxInt, unsigned
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{name: "SRLconst", argLength: 1, reg: gp11, asm: "SRL", aux: "Int32"}, // arg0 >> auxInt, unsigned, 0 <= auxInt < 32
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{name: "SRA", argLength: 2, reg: gp21, asm: "SRA"}, // arg0 >> arg1, signed, shift amount is mod 256
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{name: "SRAconst", argLength: 1, reg: gp11, asm: "SRA", aux: "Int32"}, // arg0 >> auxInt, signed
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{name: "SRAconst", argLength: 1, reg: gp11, asm: "SRA", aux: "Int32"}, // arg0 >> auxInt, signed, 0 <= auxInt < 32
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{name: "SRR", argLength: 2, reg: gp21}, // arg0 right rotate by arg1 bits
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{name: "SRRconst", argLength: 1, reg: gp11, aux: "Int32"}, // arg0 right rotate by auxInt bits
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{name: "SRRconst", argLength: 1, reg: gp11, aux: "Int32"}, // arg0 right rotate by auxInt bits, 0 <= auxInt < 32
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// auxInt for all of these satisfy 0 <= auxInt < 32
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{name: "ADDshiftLL", argLength: 2, reg: gp21, asm: "ADD", aux: "Int32"}, // arg0 + arg1<<auxInt
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{name: "ADDshiftRL", argLength: 2, reg: gp21, asm: "ADD", aux: "Int32"}, // arg0 + arg1>>auxInt, unsigned shift
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{name: "ADDshiftRA", argLength: 2, reg: gp21, asm: "ADD", aux: "Int32"}, // arg0 + arg1>>auxInt, signed shift
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@ -105,7 +105,7 @@ var genericOps = []opData{
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// For shifts, AxB means the shifted value has A bits and the shift amount has B bits.
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// Shift amounts are considered unsigned.
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// If arg1 is known to be less than the number of bits in arg0,
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// If arg1 is known to be nonnegative and less than the number of bits in arg0,
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// then auxInt may be set to 1.
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// This enables better code generation on some platforms.
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{name: "Lsh8x8", argLength: 2, aux: "Bool"}, // arg0 << arg1
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@ -1114,6 +1114,7 @@ func rewriteValueARM_OpARMADCshiftLLreg(v *Value) bool {
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return true
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}
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// match: (ADCshiftLLreg x y (MOVWconst [c]) flags)
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// cond: 0 <= c && c < 32
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// result: (ADCshiftLL x y [c] flags)
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for {
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x := v_0
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@ -1123,6 +1124,9 @@ func rewriteValueARM_OpARMADCshiftLLreg(v *Value) bool {
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}
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c := auxIntToInt32(v_2.AuxInt)
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flags := v_3
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if !(0 <= c && c < 32) {
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break
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}
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v.reset(OpARMADCshiftLL)
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v.AuxInt = int32ToAuxInt(c)
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v.AddArg3(x, y, flags)
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@ -1194,6 +1198,7 @@ func rewriteValueARM_OpARMADCshiftRAreg(v *Value) bool {
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return true
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}
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// match: (ADCshiftRAreg x y (MOVWconst [c]) flags)
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// cond: 0 <= c && c < 32
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// result: (ADCshiftRA x y [c] flags)
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for {
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x := v_0
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@ -1203,6 +1208,9 @@ func rewriteValueARM_OpARMADCshiftRAreg(v *Value) bool {
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}
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c := auxIntToInt32(v_2.AuxInt)
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flags := v_3
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if !(0 <= c && c < 32) {
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break
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}
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v.reset(OpARMADCshiftRA)
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v.AuxInt = int32ToAuxInt(c)
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v.AddArg3(x, y, flags)
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@ -1274,6 +1282,7 @@ func rewriteValueARM_OpARMADCshiftRLreg(v *Value) bool {
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return true
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}
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// match: (ADCshiftRLreg x y (MOVWconst [c]) flags)
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// cond: 0 <= c && c < 32
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// result: (ADCshiftRL x y [c] flags)
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for {
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x := v_0
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@ -1283,6 +1292,9 @@ func rewriteValueARM_OpARMADCshiftRLreg(v *Value) bool {
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}
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c := auxIntToInt32(v_2.AuxInt)
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flags := v_3
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if !(0 <= c && c < 32) {
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break
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}
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v.reset(OpARMADCshiftRL)
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v.AuxInt = int32ToAuxInt(c)
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v.AddArg3(x, y, flags)
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@ -1735,6 +1747,7 @@ func rewriteValueARM_OpARMADDSshiftLLreg(v *Value) bool {
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return true
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}
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// match: (ADDSshiftLLreg x y (MOVWconst [c]))
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// cond: 0 <= c && c < 32
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// result: (ADDSshiftLL x y [c])
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for {
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x := v_0
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@ -1743,6 +1756,9 @@ func rewriteValueARM_OpARMADDSshiftLLreg(v *Value) bool {
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break
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}
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c := auxIntToInt32(v_2.AuxInt)
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if !(0 <= c && c < 32) {
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break
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}
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v.reset(OpARMADDSshiftLL)
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v.AuxInt = int32ToAuxInt(c)
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v.AddArg2(x, y)
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@ -1809,6 +1825,7 @@ func rewriteValueARM_OpARMADDSshiftRAreg(v *Value) bool {
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return true
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}
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// match: (ADDSshiftRAreg x y (MOVWconst [c]))
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// cond: 0 <= c && c < 32
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// result: (ADDSshiftRA x y [c])
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for {
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x := v_0
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@ -1817,6 +1834,9 @@ func rewriteValueARM_OpARMADDSshiftRAreg(v *Value) bool {
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break
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}
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c := auxIntToInt32(v_2.AuxInt)
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if !(0 <= c && c < 32) {
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break
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}
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v.reset(OpARMADDSshiftRA)
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v.AuxInt = int32ToAuxInt(c)
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v.AddArg2(x, y)
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@ -1883,6 +1903,7 @@ func rewriteValueARM_OpARMADDSshiftRLreg(v *Value) bool {
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return true
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}
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// match: (ADDSshiftRLreg x y (MOVWconst [c]))
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// cond: 0 <= c && c < 32
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// result: (ADDSshiftRL x y [c])
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for {
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x := v_0
|
||||
|
|
@ -1891,6 +1912,9 @@ func rewriteValueARM_OpARMADDSshiftRLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMADDSshiftRL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -2119,6 +2143,7 @@ func rewriteValueARM_OpARMADDshiftLLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (ADDshiftLLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (ADDshiftLL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -2127,6 +2152,9 @@ func rewriteValueARM_OpARMADDshiftLLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMADDshiftLL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -2193,6 +2221,7 @@ func rewriteValueARM_OpARMADDshiftRAreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (ADDshiftRAreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (ADDshiftRA x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -2201,6 +2230,9 @@ func rewriteValueARM_OpARMADDshiftRAreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMADDshiftRA)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -2283,6 +2315,7 @@ func rewriteValueARM_OpARMADDshiftRLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (ADDshiftRLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (ADDshiftRL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -2291,6 +2324,9 @@ func rewriteValueARM_OpARMADDshiftRLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMADDshiftRL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -2648,6 +2684,7 @@ func rewriteValueARM_OpARMANDshiftLLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (ANDshiftLLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (ANDshiftLL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -2656,6 +2693,9 @@ func rewriteValueARM_OpARMANDshiftLLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMANDshiftLL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -2737,6 +2777,7 @@ func rewriteValueARM_OpARMANDshiftRAreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (ANDshiftRAreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (ANDshiftRA x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -2745,6 +2786,9 @@ func rewriteValueARM_OpARMANDshiftRAreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMANDshiftRA)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -2826,6 +2870,7 @@ func rewriteValueARM_OpARMANDshiftRLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (ANDshiftRLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (ANDshiftRL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -2834,6 +2879,9 @@ func rewriteValueARM_OpARMANDshiftRLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMANDshiftRL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -3102,6 +3150,7 @@ func rewriteValueARM_OpARMBICshiftLLreg(v *Value) bool {
|
|||
v_1 := v.Args[1]
|
||||
v_0 := v.Args[0]
|
||||
// match: (BICshiftLLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (BICshiftLL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -3110,6 +3159,9 @@ func rewriteValueARM_OpARMBICshiftLLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMBICshiftLL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -3156,6 +3208,7 @@ func rewriteValueARM_OpARMBICshiftRAreg(v *Value) bool {
|
|||
v_1 := v.Args[1]
|
||||
v_0 := v.Args[0]
|
||||
// match: (BICshiftRAreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (BICshiftRA x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -3164,6 +3217,9 @@ func rewriteValueARM_OpARMBICshiftRAreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMBICshiftRA)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -3210,6 +3266,7 @@ func rewriteValueARM_OpARMBICshiftRLreg(v *Value) bool {
|
|||
v_1 := v.Args[1]
|
||||
v_0 := v.Args[0]
|
||||
// match: (BICshiftRLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (BICshiftRL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -3218,6 +3275,9 @@ func rewriteValueARM_OpARMBICshiftRLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMBICshiftRL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -3420,6 +3480,7 @@ func rewriteValueARM_OpARMCMNshiftLLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (CMNshiftLLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (CMNshiftLL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -3428,6 +3489,9 @@ func rewriteValueARM_OpARMCMNshiftLLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMCMNshiftLL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -3494,6 +3558,7 @@ func rewriteValueARM_OpARMCMNshiftRAreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (CMNshiftRAreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (CMNshiftRA x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -3502,6 +3567,9 @@ func rewriteValueARM_OpARMCMNshiftRAreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMCMNshiftRA)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -3568,6 +3636,7 @@ func rewriteValueARM_OpARMCMNshiftRLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (CMNshiftRLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (CMNshiftRL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -3576,6 +3645,9 @@ func rewriteValueARM_OpARMCMNshiftRLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMCMNshiftRL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -4073,6 +4145,7 @@ func rewriteValueARM_OpARMCMPshiftLLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (CMPshiftLLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (CMPshiftLL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -4081,6 +4154,9 @@ func rewriteValueARM_OpARMCMPshiftLLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMCMPshiftLL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -4151,6 +4227,7 @@ func rewriteValueARM_OpARMCMPshiftRAreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (CMPshiftRAreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (CMPshiftRA x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -4159,6 +4236,9 @@ func rewriteValueARM_OpARMCMPshiftRAreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMCMPshiftRA)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -4229,6 +4309,7 @@ func rewriteValueARM_OpARMCMPshiftRLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (CMPshiftRLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (CMPshiftRL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -4237,6 +4318,9 @@ func rewriteValueARM_OpARMCMPshiftRLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMCMPshiftRL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -8069,6 +8153,7 @@ func rewriteValueARM_OpARMMVNshiftLLreg(v *Value) bool {
|
|||
v_1 := v.Args[1]
|
||||
v_0 := v.Args[0]
|
||||
// match: (MVNshiftLLreg x (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (MVNshiftLL x [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -8076,6 +8161,9 @@ func rewriteValueARM_OpARMMVNshiftLLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_1.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMMVNshiftLL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg(x)
|
||||
|
|
@ -8103,6 +8191,7 @@ func rewriteValueARM_OpARMMVNshiftRAreg(v *Value) bool {
|
|||
v_1 := v.Args[1]
|
||||
v_0 := v.Args[0]
|
||||
// match: (MVNshiftRAreg x (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (MVNshiftRA x [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -8110,6 +8199,9 @@ func rewriteValueARM_OpARMMVNshiftRAreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_1.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMMVNshiftRA)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg(x)
|
||||
|
|
@ -8137,6 +8229,7 @@ func rewriteValueARM_OpARMMVNshiftRLreg(v *Value) bool {
|
|||
v_1 := v.Args[1]
|
||||
v_0 := v.Args[0]
|
||||
// match: (MVNshiftRLreg x (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (MVNshiftRL x [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -8144,6 +8237,9 @@ func rewriteValueARM_OpARMMVNshiftRLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_1.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMMVNshiftRL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg(x)
|
||||
|
|
@ -8563,6 +8659,7 @@ func rewriteValueARM_OpARMORshiftLLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (ORshiftLLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (ORshiftLL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -8571,6 +8668,9 @@ func rewriteValueARM_OpARMORshiftLLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMORshiftLL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -8652,6 +8752,7 @@ func rewriteValueARM_OpARMORshiftRAreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (ORshiftRAreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (ORshiftRA x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -8660,6 +8761,9 @@ func rewriteValueARM_OpARMORshiftRAreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMORshiftRA)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -8757,6 +8861,7 @@ func rewriteValueARM_OpARMORshiftRLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (ORshiftRLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (ORshiftRL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -8765,6 +8870,9 @@ func rewriteValueARM_OpARMORshiftRLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMORshiftRL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -9052,6 +9160,7 @@ func rewriteValueARM_OpARMRSBSshiftLLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (RSBSshiftLLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (RSBSshiftLL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -9060,6 +9169,9 @@ func rewriteValueARM_OpARMRSBSshiftLLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMRSBSshiftLL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -9126,6 +9238,7 @@ func rewriteValueARM_OpARMRSBSshiftRAreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (RSBSshiftRAreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (RSBSshiftRA x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -9134,6 +9247,9 @@ func rewriteValueARM_OpARMRSBSshiftRAreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMRSBSshiftRA)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -9200,6 +9316,7 @@ func rewriteValueARM_OpARMRSBSshiftRLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (RSBSshiftRLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (RSBSshiftRL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -9208,6 +9325,9 @@ func rewriteValueARM_OpARMRSBSshiftRLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMRSBSshiftRL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -9347,6 +9467,7 @@ func rewriteValueARM_OpARMRSBshiftLLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (RSBshiftLLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (RSBshiftLL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -9355,6 +9476,9 @@ func rewriteValueARM_OpARMRSBshiftLLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMRSBshiftLL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -9436,6 +9560,7 @@ func rewriteValueARM_OpARMRSBshiftRAreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (RSBshiftRAreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (RSBshiftRA x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -9444,6 +9569,9 @@ func rewriteValueARM_OpARMRSBshiftRAreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMRSBshiftRA)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -9525,6 +9653,7 @@ func rewriteValueARM_OpARMRSBshiftRLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (RSBshiftRLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (RSBshiftRL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -9533,6 +9662,9 @@ func rewriteValueARM_OpARMRSBshiftRLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMRSBshiftRL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -9639,6 +9771,7 @@ func rewriteValueARM_OpARMRSCshiftLLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (RSCshiftLLreg x y (MOVWconst [c]) flags)
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (RSCshiftLL x y [c] flags)
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -9648,6 +9781,9 @@ func rewriteValueARM_OpARMRSCshiftLLreg(v *Value) bool {
|
|||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
flags := v_3
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMRSCshiftLL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg3(x, y, flags)
|
||||
|
|
@ -9719,6 +9855,7 @@ func rewriteValueARM_OpARMRSCshiftRAreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (RSCshiftRAreg x y (MOVWconst [c]) flags)
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (RSCshiftRA x y [c] flags)
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -9728,6 +9865,9 @@ func rewriteValueARM_OpARMRSCshiftRAreg(v *Value) bool {
|
|||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
flags := v_3
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMRSCshiftRA)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg3(x, y, flags)
|
||||
|
|
@ -9799,6 +9939,7 @@ func rewriteValueARM_OpARMRSCshiftRLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (RSCshiftRLreg x y (MOVWconst [c]) flags)
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (RSCshiftRL x y [c] flags)
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -9808,6 +9949,9 @@ func rewriteValueARM_OpARMRSCshiftRLreg(v *Value) bool {
|
|||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
flags := v_3
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMRSCshiftRL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg3(x, y, flags)
|
||||
|
|
@ -10122,6 +10266,7 @@ func rewriteValueARM_OpARMSBCshiftLLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (SBCshiftLLreg x y (MOVWconst [c]) flags)
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (SBCshiftLL x y [c] flags)
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -10131,6 +10276,9 @@ func rewriteValueARM_OpARMSBCshiftLLreg(v *Value) bool {
|
|||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
flags := v_3
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMSBCshiftLL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg3(x, y, flags)
|
||||
|
|
@ -10202,6 +10350,7 @@ func rewriteValueARM_OpARMSBCshiftRAreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (SBCshiftRAreg x y (MOVWconst [c]) flags)
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (SBCshiftRA x y [c] flags)
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -10211,6 +10360,9 @@ func rewriteValueARM_OpARMSBCshiftRAreg(v *Value) bool {
|
|||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
flags := v_3
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMSBCshiftRA)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg3(x, y, flags)
|
||||
|
|
@ -10282,6 +10434,7 @@ func rewriteValueARM_OpARMSBCshiftRLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (SBCshiftRLreg x y (MOVWconst [c]) flags)
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (SBCshiftRL x y [c] flags)
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -10291,6 +10444,9 @@ func rewriteValueARM_OpARMSBCshiftRLreg(v *Value) bool {
|
|||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
flags := v_3
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMSBCshiftRL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg3(x, y, flags)
|
||||
|
|
@ -10302,15 +10458,19 @@ func rewriteValueARM_OpARMSLL(v *Value) bool {
|
|||
v_1 := v.Args[1]
|
||||
v_0 := v.Args[0]
|
||||
// match: (SLL x (MOVWconst [c]))
|
||||
// result: (SLLconst x [c&31])
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (SLLconst x [c])
|
||||
for {
|
||||
x := v_0
|
||||
if v_1.Op != OpARMMOVWconst {
|
||||
break
|
||||
}
|
||||
c := auxIntToInt32(v_1.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMSLLconst)
|
||||
v.AuxInt = int32ToAuxInt(c & 31)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
|
|
@ -10336,15 +10496,19 @@ func rewriteValueARM_OpARMSRA(v *Value) bool {
|
|||
v_1 := v.Args[1]
|
||||
v_0 := v.Args[0]
|
||||
// match: (SRA x (MOVWconst [c]))
|
||||
// result: (SRAconst x [c&31])
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (SRAconst x [c])
|
||||
for {
|
||||
x := v_0
|
||||
if v_1.Op != OpARMMOVWconst {
|
||||
break
|
||||
}
|
||||
c := auxIntToInt32(v_1.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMSRAconst)
|
||||
v.AuxInt = int32ToAuxInt(c & 31)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
|
|
@ -10428,15 +10592,19 @@ func rewriteValueARM_OpARMSRL(v *Value) bool {
|
|||
v_1 := v.Args[1]
|
||||
v_0 := v.Args[0]
|
||||
// match: (SRL x (MOVWconst [c]))
|
||||
// result: (SRLconst x [c&31])
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (SRLconst x [c])
|
||||
for {
|
||||
x := v_0
|
||||
if v_1.Op != OpARMMOVWconst {
|
||||
break
|
||||
}
|
||||
c := auxIntToInt32(v_1.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMSRLconst)
|
||||
v.AuxInt = int32ToAuxInt(c & 31)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
|
|
@ -11014,6 +11182,7 @@ func rewriteValueARM_OpARMSUBSshiftLLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (SUBSshiftLLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (SUBSshiftLL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -11022,6 +11191,9 @@ func rewriteValueARM_OpARMSUBSshiftLLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMSUBSshiftLL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -11088,6 +11260,7 @@ func rewriteValueARM_OpARMSUBSshiftRAreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (SUBSshiftRAreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (SUBSshiftRA x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -11096,6 +11269,9 @@ func rewriteValueARM_OpARMSUBSshiftRAreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMSUBSshiftRA)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -11162,6 +11338,7 @@ func rewriteValueARM_OpARMSUBSshiftRLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (SUBSshiftRLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (SUBSshiftRL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -11170,6 +11347,9 @@ func rewriteValueARM_OpARMSUBSshiftRLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMSUBSshiftRL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -11363,6 +11543,7 @@ func rewriteValueARM_OpARMSUBshiftLLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (SUBshiftLLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (SUBshiftLL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -11371,6 +11552,9 @@ func rewriteValueARM_OpARMSUBshiftLLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMSUBshiftLL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -11452,6 +11636,7 @@ func rewriteValueARM_OpARMSUBshiftRAreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (SUBshiftRAreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (SUBshiftRA x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -11460,6 +11645,9 @@ func rewriteValueARM_OpARMSUBshiftRAreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMSUBshiftRA)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -11541,6 +11729,7 @@ func rewriteValueARM_OpARMSUBshiftRLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (SUBshiftRLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (SUBshiftRL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -11549,6 +11738,9 @@ func rewriteValueARM_OpARMSUBshiftRLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMSUBshiftRL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -11751,6 +11943,7 @@ func rewriteValueARM_OpARMTEQshiftLLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (TEQshiftLLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (TEQshiftLL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -11759,6 +11952,9 @@ func rewriteValueARM_OpARMTEQshiftLLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMTEQshiftLL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -11825,6 +12021,7 @@ func rewriteValueARM_OpARMTEQshiftRAreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (TEQshiftRAreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (TEQshiftRA x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -11833,6 +12030,9 @@ func rewriteValueARM_OpARMTEQshiftRAreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMTEQshiftRA)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -11899,6 +12099,7 @@ func rewriteValueARM_OpARMTEQshiftRLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (TEQshiftRLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (TEQshiftRL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -11907,6 +12108,9 @@ func rewriteValueARM_OpARMTEQshiftRLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMTEQshiftRL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -12109,6 +12313,7 @@ func rewriteValueARM_OpARMTSTshiftLLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (TSTshiftLLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (TSTshiftLL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -12117,6 +12322,9 @@ func rewriteValueARM_OpARMTSTshiftLLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMTSTshiftLL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -12183,6 +12391,7 @@ func rewriteValueARM_OpARMTSTshiftRAreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (TSTshiftRAreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (TSTshiftRA x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -12191,6 +12400,9 @@ func rewriteValueARM_OpARMTSTshiftRAreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMTSTshiftRA)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -12257,6 +12469,7 @@ func rewriteValueARM_OpARMTSTshiftRLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (TSTshiftRLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (TSTshiftRL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -12265,6 +12478,9 @@ func rewriteValueARM_OpARMTSTshiftRLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMTSTshiftRL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -12584,6 +12800,7 @@ func rewriteValueARM_OpARMXORshiftLLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (XORshiftLLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (XORshiftLL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -12592,6 +12809,9 @@ func rewriteValueARM_OpARMXORshiftLLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMXORshiftLL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -12673,6 +12893,7 @@ func rewriteValueARM_OpARMXORshiftRAreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (XORshiftRAreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (XORshiftRA x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -12681,6 +12902,9 @@ func rewriteValueARM_OpARMXORshiftRAreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMXORshiftRA)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
@ -12778,6 +13002,7 @@ func rewriteValueARM_OpARMXORshiftRLreg(v *Value) bool {
|
|||
return true
|
||||
}
|
||||
// match: (XORshiftRLreg x y (MOVWconst [c]))
|
||||
// cond: 0 <= c && c < 32
|
||||
// result: (XORshiftRL x y [c])
|
||||
for {
|
||||
x := v_0
|
||||
|
|
@ -12786,6 +13011,9 @@ func rewriteValueARM_OpARMXORshiftRLreg(v *Value) bool {
|
|||
break
|
||||
}
|
||||
c := auxIntToInt32(v_2.AuxInt)
|
||||
if !(0 <= c && c < 32) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMXORshiftRL)
|
||||
v.AuxInt = int32ToAuxInt(c)
|
||||
v.AddArg2(x, y)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,21 @@
|
|||
// run
|
||||
|
||||
// Copyright 2021 The Go Authors. All rights reserved.
|
||||
// Use of this source code is governed by a BSD-style
|
||||
// license that can be found in the LICENSE file.
|
||||
|
||||
package main
|
||||
|
||||
import "fmt"
|
||||
|
||||
//go:noinline
|
||||
func f(x uint64) uint64 {
|
||||
s := "\x04"
|
||||
c := s[0]
|
||||
return x << c << 4
|
||||
}
|
||||
func main() {
|
||||
if want, got := uint64(1<<8), f(1); want != got {
|
||||
panic(fmt.Sprintf("want %x got %x", want, got))
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue