mirror of https://github.com/golang/go.git
cmd/compile: regalloc enforces 2-address instructions
Instead of being a hint, resultInArg0 is now enforced by regalloc. This allows us to delete all the code from amd64/ssa.go which deals with converting from a semantically three-address instruction into some copies plus a two-address instruction. Change-Id: Id4f39a80be4b678718bfd42a229f9094ab6ecd7c Reviewed-on: https://go-review.googlesource.com/21816 Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
This commit is contained in:
Keith Randall
parent
6b33b0e98e
commit
0004f34cef
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@ -192,74 +192,23 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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}
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// 2-address opcode arithmetic, symmetric
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case ssa.OpAMD64ADDSS, ssa.OpAMD64ADDSD,
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// 2-address opcode arithmetic
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case ssa.OpAMD64SUBQ, ssa.OpAMD64SUBL, ssa.OpAMD64SUBW, ssa.OpAMD64SUBB,
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ssa.OpAMD64MULQ, ssa.OpAMD64MULL, ssa.OpAMD64MULW, ssa.OpAMD64MULB,
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ssa.OpAMD64ANDQ, ssa.OpAMD64ANDL, ssa.OpAMD64ANDW, ssa.OpAMD64ANDB,
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ssa.OpAMD64ORQ, ssa.OpAMD64ORL, ssa.OpAMD64ORW, ssa.OpAMD64ORB,
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ssa.OpAMD64XORQ, ssa.OpAMD64XORL, ssa.OpAMD64XORW, ssa.OpAMD64XORB,
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ssa.OpAMD64MULQ, ssa.OpAMD64MULL, ssa.OpAMD64MULW, ssa.OpAMD64MULB,
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ssa.OpAMD64MULSS, ssa.OpAMD64MULSD, ssa.OpAMD64PXOR:
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ssa.OpAMD64SHLQ, ssa.OpAMD64SHLL, ssa.OpAMD64SHLW, ssa.OpAMD64SHLB,
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ssa.OpAMD64SHRQ, ssa.OpAMD64SHRL, ssa.OpAMD64SHRW, ssa.OpAMD64SHRB,
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ssa.OpAMD64SARQ, ssa.OpAMD64SARL, ssa.OpAMD64SARW, ssa.OpAMD64SARB,
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ssa.OpAMD64ADDSS, ssa.OpAMD64ADDSD, ssa.OpAMD64SUBSS, ssa.OpAMD64SUBSD,
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ssa.OpAMD64MULSS, ssa.OpAMD64MULSD, ssa.OpAMD64DIVSS, ssa.OpAMD64DIVSD,
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ssa.OpAMD64PXOR:
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r := gc.SSARegNum(v)
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x := gc.SSARegNum(v.Args[0])
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y := gc.SSARegNum(v.Args[1])
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if x != r && y != r {
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opregreg(moveByType(v.Type), r, x)
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x = r
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if r != gc.SSARegNum(v.Args[0]) {
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v.Fatalf("input[0] and output not in same register %s", v.LongString())
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}
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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if x == r {
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p.From.Reg = y
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} else {
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p.From.Reg = x
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}
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// 2-address opcode arithmetic, not symmetric
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case ssa.OpAMD64SUBQ, ssa.OpAMD64SUBL, ssa.OpAMD64SUBW, ssa.OpAMD64SUBB:
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r := gc.SSARegNum(v)
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x := gc.SSARegNum(v.Args[0])
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y := gc.SSARegNum(v.Args[1])
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var neg bool
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if y == r {
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// compute -(y-x) instead
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x, y = y, x
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neg = true
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}
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if x != r {
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opregreg(moveByType(v.Type), r, x)
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}
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opregreg(v.Op.Asm(), r, y)
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if neg {
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if v.Op == ssa.OpAMD64SUBQ {
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p := gc.Prog(x86.ANEGQ)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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} else { // Avoids partial registers write
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p := gc.Prog(x86.ANEGL)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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}
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}
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case ssa.OpAMD64SUBSS, ssa.OpAMD64SUBSD, ssa.OpAMD64DIVSS, ssa.OpAMD64DIVSD:
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r := gc.SSARegNum(v)
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x := gc.SSARegNum(v.Args[0])
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y := gc.SSARegNum(v.Args[1])
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if y == r && x != r {
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// r/y := x op r/y, need to preserve x and rewrite to
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// r/y := r/y op x15
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x15 := int16(x86.REG_X15)
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// register move y to x15
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// register move x to y
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// rename y with x15
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opregreg(moveByType(v.Type), x15, y)
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opregreg(moveByType(v.Type), r, x)
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y = x15
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} else if x != r {
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opregreg(moveByType(v.Type), r, x)
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}
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opregreg(v.Op.Asm(), r, y)
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opregreg(v.Op.Asm(), r, gc.SSARegNum(v.Args[1]))
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case ssa.OpAMD64DIVQ, ssa.OpAMD64DIVL, ssa.OpAMD64DIVW,
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ssa.OpAMD64DIVQU, ssa.OpAMD64DIVLU, ssa.OpAMD64DIVWU,
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@ -372,47 +321,20 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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// Do a 64-bit add, the overflow goes into the carry.
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// Shift right once and pull the carry back into the 63rd bit.
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r := gc.SSARegNum(v)
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x := gc.SSARegNum(v.Args[0])
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y := gc.SSARegNum(v.Args[1])
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if x != r && y != r {
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opregreg(moveByType(v.Type), r, x)
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x = r
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if r != gc.SSARegNum(v.Args[0]) {
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v.Fatalf("input[0] and output not in same register %s", v.LongString())
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}
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p := gc.Prog(x86.AADDQ)
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p.From.Type = obj.TYPE_REG
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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if x == r {
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p.From.Reg = y
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} else {
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p.From.Reg = x
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}
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p.From.Reg = gc.SSARegNum(v.Args[1])
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p = gc.Prog(x86.ARCRQ)
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = 1
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.OpAMD64SHLQ, ssa.OpAMD64SHLL, ssa.OpAMD64SHLW, ssa.OpAMD64SHLB,
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ssa.OpAMD64SHRQ, ssa.OpAMD64SHRL, ssa.OpAMD64SHRW, ssa.OpAMD64SHRB,
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ssa.OpAMD64SARQ, ssa.OpAMD64SARL, ssa.OpAMD64SARW, ssa.OpAMD64SARB:
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x := gc.SSARegNum(v.Args[0])
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r := gc.SSARegNum(v)
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if x != r {
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if r == x86.REG_CX {
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v.Fatalf("can't implement %s, target and shift both in CX", v.LongString())
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}
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p := gc.Prog(moveByType(v.Type))
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p.From.Type = obj.TYPE_REG
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p.From.Reg = x
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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}
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = gc.SSARegNum(v.Args[1]) // should be CX
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.OpAMD64ADDQconst, ssa.OpAMD64ADDLconst, ssa.OpAMD64ADDWconst, ssa.OpAMD64ADDBconst:
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r := gc.SSARegNum(v)
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a := gc.SSARegNum(v.Args[0])
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@ -433,7 +355,8 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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return
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} else if v.AuxInt == -1 {
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}
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if v.AuxInt == -1 {
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var asm obj.As
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if v.Op == ssa.OpAMD64ADDQconst {
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asm = x86.ADECQ
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@ -444,14 +367,13 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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return
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} else {
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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return
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}
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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return
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}
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var asm obj.As
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if v.Op == ssa.OpAMD64ADDQconst {
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@ -469,17 +391,11 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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case ssa.OpAMD64CMOVQEQconst, ssa.OpAMD64CMOVLEQconst, ssa.OpAMD64CMOVWEQconst,
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ssa.OpAMD64CMOVQNEconst, ssa.OpAMD64CMOVLNEconst, ssa.OpAMD64CMOVWNEconst:
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r := gc.SSARegNum(v)
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x := gc.SSARegNum(v.Args[0])
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// Arg0 is in/out, move in to out if not already same
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if r != x {
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p := gc.Prog(moveByType(v.Type))
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p.From.Type = obj.TYPE_REG
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p.From.Reg = x
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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if r != gc.SSARegNum(v.Args[0]) {
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v.Fatalf("input[0] and output not in same register %s", v.LongString())
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}
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// Constant into AX, after arg0 movement in case arg0 is in AX
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// Constant into AX
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p := gc.Prog(moveByType(v.Type))
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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@ -494,13 +410,8 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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case ssa.OpAMD64MULQconst, ssa.OpAMD64MULLconst, ssa.OpAMD64MULWconst, ssa.OpAMD64MULBconst:
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r := gc.SSARegNum(v)
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x := gc.SSARegNum(v.Args[0])
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if r != x {
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p := gc.Prog(moveByType(v.Type))
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p.From.Type = obj.TYPE_REG
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p.From.Reg = x
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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if r != gc.SSARegNum(v.Args[0]) {
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v.Fatalf("input[0] and output not in same register %s", v.LongString())
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}
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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@ -508,87 +419,22 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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// TODO: Teach doasm to compile the three-address multiply imul $c, r1, r2
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// instead of using the MOVQ above.
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// then we don't need to use resultInArg0 for these ops.
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//p.From3 = new(obj.Addr)
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//p.From3.Type = obj.TYPE_REG
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//p.From3.Reg = gc.SSARegNum(v.Args[0])
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case ssa.OpAMD64SUBQconst, ssa.OpAMD64SUBLconst, ssa.OpAMD64SUBWconst, ssa.OpAMD64SUBBconst:
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x := gc.SSARegNum(v.Args[0])
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r := gc.SSARegNum(v)
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// We have 3-op add (lea), so transforming a = b - const into
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// a = b + (- const), saves us 1 instruction. We can't fit
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// - (-1 << 31) into 4 bytes offset in lea.
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// We handle 2-address just fine below.
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if v.AuxInt == -1<<31 || x == r {
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if x != r {
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// This code compensates for the fact that the register allocator
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// doesn't understand 2-address instructions yet. TODO: fix that.
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p := gc.Prog(moveByType(v.Type))
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p.From.Type = obj.TYPE_REG
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p.From.Reg = x
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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}
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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} else if x == r && v.AuxInt == -1 {
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var asm obj.As
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// x = x - (-1) is the same as x++
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// See OpAMD64ADDQconst comments about inc vs add $1,reg
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if v.Op == ssa.OpAMD64SUBQconst {
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asm = x86.AINCQ
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} else {
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asm = x86.AINCL
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}
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p := gc.Prog(asm)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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} else if x == r && v.AuxInt == 1 {
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var asm obj.As
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if v.Op == ssa.OpAMD64SUBQconst {
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asm = x86.ADECQ
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} else {
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asm = x86.ADECL
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}
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p := gc.Prog(asm)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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} else {
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var asm obj.As
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if v.Op == ssa.OpAMD64SUBQconst {
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asm = x86.ALEAQ
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} else {
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asm = x86.ALEAL
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}
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p := gc.Prog(asm)
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = x
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p.From.Offset = -v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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}
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case ssa.OpAMD64ANDQconst, ssa.OpAMD64ANDLconst, ssa.OpAMD64ANDWconst, ssa.OpAMD64ANDBconst,
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case ssa.OpAMD64SUBQconst, ssa.OpAMD64SUBLconst, ssa.OpAMD64SUBWconst, ssa.OpAMD64SUBBconst,
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ssa.OpAMD64ANDQconst, ssa.OpAMD64ANDLconst, ssa.OpAMD64ANDWconst, ssa.OpAMD64ANDBconst,
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ssa.OpAMD64ORQconst, ssa.OpAMD64ORLconst, ssa.OpAMD64ORWconst, ssa.OpAMD64ORBconst,
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ssa.OpAMD64XORQconst, ssa.OpAMD64XORLconst, ssa.OpAMD64XORWconst, ssa.OpAMD64XORBconst,
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ssa.OpAMD64SHLQconst, ssa.OpAMD64SHLLconst, ssa.OpAMD64SHLWconst,
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ssa.OpAMD64SHLBconst, ssa.OpAMD64SHRQconst, ssa.OpAMD64SHRLconst, ssa.OpAMD64SHRWconst,
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ssa.OpAMD64SHRBconst, ssa.OpAMD64SARQconst, ssa.OpAMD64SARLconst, ssa.OpAMD64SARWconst,
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ssa.OpAMD64SARBconst, ssa.OpAMD64ROLQconst, ssa.OpAMD64ROLLconst, ssa.OpAMD64ROLWconst,
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ssa.OpAMD64ROLBconst:
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// This code compensates for the fact that the register allocator
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// doesn't understand 2-address instructions yet. TODO: fix that.
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x := gc.SSARegNum(v.Args[0])
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ssa.OpAMD64SHLQconst, ssa.OpAMD64SHLLconst, ssa.OpAMD64SHLWconst, ssa.OpAMD64SHLBconst,
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ssa.OpAMD64SHRQconst, ssa.OpAMD64SHRLconst, ssa.OpAMD64SHRWconst, ssa.OpAMD64SHRBconst,
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ssa.OpAMD64SARQconst, ssa.OpAMD64SARLconst, ssa.OpAMD64SARWconst, ssa.OpAMD64SARBconst,
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ssa.OpAMD64ROLQconst, ssa.OpAMD64ROLLconst, ssa.OpAMD64ROLWconst, ssa.OpAMD64ROLBconst:
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r := gc.SSARegNum(v)
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if x != r {
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p := gc.Prog(moveByType(v.Type))
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p.From.Type = obj.TYPE_REG
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p.From.Reg = x
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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if r != gc.SSARegNum(v.Args[0]) {
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v.Fatalf("input[0] and output not in same register %s", v.LongString())
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}
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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@ -821,9 +667,6 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Offset = v.AuxInt
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case ssa.OpCopy, ssa.OpAMD64MOVQconvert: // TODO: use MOVQreg for reg->reg copies instead of OpCopy?
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if v.Type.IsMemory() {
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return
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}
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x := gc.SSARegNum(v.Args[0])
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y := gc.SSARegNum(v)
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if x != y {
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@ -969,14 +812,9 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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case ssa.OpAMD64NEGQ, ssa.OpAMD64NEGL, ssa.OpAMD64NEGW, ssa.OpAMD64NEGB,
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ssa.OpAMD64BSWAPQ, ssa.OpAMD64BSWAPL,
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ssa.OpAMD64NOTQ, ssa.OpAMD64NOTL, ssa.OpAMD64NOTW, ssa.OpAMD64NOTB:
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x := gc.SSARegNum(v.Args[0])
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r := gc.SSARegNum(v)
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if x != r {
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p := gc.Prog(moveByType(v.Type))
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p.From.Type = obj.TYPE_REG
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p.From.Reg = x
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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if r != gc.SSARegNum(v.Args[0]) {
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v.Fatalf("input[0] and output not in same register %s", v.LongString())
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}
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p := gc.Prog(v.Op.Asm())
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p.To.Type = obj.TYPE_REG
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@ -1273,6 +1273,12 @@
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(XORWconst [c] x) && int16(c)==0 -> x
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(XORBconst [c] x) && int8(c)==0 -> x
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// Convert constant subtracts to constant adds
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(SUBQconst [c] x) && c != -(1<<31) -> (ADDQconst [-c] x)
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(SUBLconst [c] x) -> (ADDLconst [int64(int32(-c))] x)
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(SUBWconst [c] x) -> (ADDWconst [int64(int16(-c))] x)
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(SUBBconst [c] x) -> (ADDBconst [int64(int8(-c))] x)
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// generic constant folding
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// TODO: more of this
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(ADDQconst [c] (MOVQconst [d])) -> (MOVQconst [c+d])
|
||||
|
|
|
|||
|
|
@ -111,12 +111,14 @@ func init() {
|
|||
// Common regInfo
|
||||
var (
|
||||
gp01 = regInfo{inputs: []regMask{}, outputs: gponly}
|
||||
gp11 = regInfo{inputs: []regMask{gpsp}, outputs: gponly, clobbers: flags}
|
||||
gp11 = regInfo{inputs: []regMask{gp}, outputs: gponly, clobbers: flags}
|
||||
gp11sp = regInfo{inputs: []regMask{gpsp}, outputs: gponly, clobbers: flags}
|
||||
gp11nf = regInfo{inputs: []regMask{gpsp}, outputs: gponly} // nf: no flags clobbered
|
||||
gp11sb = regInfo{inputs: []regMask{gpspsb}, outputs: gponly}
|
||||
gp21 = regInfo{inputs: []regMask{gpsp, gpsp}, outputs: gponly, clobbers: flags}
|
||||
gp21 = regInfo{inputs: []regMask{gp, gp}, outputs: gponly, clobbers: flags}
|
||||
gp21sp = regInfo{inputs: []regMask{gpsp, gp}, outputs: gponly, clobbers: flags}
|
||||
gp21sb = regInfo{inputs: []regMask{gpspsb, gpsp}, outputs: gponly}
|
||||
gp21shift = regInfo{inputs: []regMask{gpsp, cx}, outputs: []regMask{gp &^ cx}, clobbers: flags}
|
||||
gp21shift = regInfo{inputs: []regMask{gp, cx}, outputs: []regMask{gp}, clobbers: flags}
|
||||
gp11div = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{ax},
|
||||
clobbers: dx | flags}
|
||||
gp11hmul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx},
|
||||
|
|
@ -128,8 +130,8 @@ func init() {
|
|||
gp1flags = regInfo{inputs: []regMask{gpsp}, outputs: flagsonly}
|
||||
flagsgp = regInfo{inputs: flagsonly, outputs: gponly}
|
||||
|
||||
// for CMOVconst -- uses AX to hold constant temporary. AX input is moved before temp.
|
||||
gp1flagsgp = regInfo{inputs: []regMask{gp, flags}, clobbers: ax | flags, outputs: []regMask{gp &^ ax}}
|
||||
// for CMOVconst -- uses AX to hold constant temporary.
|
||||
gp1flagsgp = regInfo{inputs: []regMask{gp &^ ax, flags}, clobbers: ax | flags, outputs: []regMask{gp &^ ax}}
|
||||
|
||||
readflags = regInfo{inputs: flagsonly, outputs: gponly}
|
||||
flagsgpax = regInfo{inputs: flagsonly, clobbers: ax | flags, outputs: []regMask{gp &^ ax}}
|
||||
|
|
@ -186,14 +188,14 @@ func init() {
|
|||
{name: "MOVSDstoreidx8", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff"}, // fp64 indexed by 8i store
|
||||
|
||||
// binary ops
|
||||
{name: "ADDQ", argLength: 2, reg: gp21, asm: "ADDQ", commutative: true, resultInArg0: true}, // arg0 + arg1
|
||||
{name: "ADDL", argLength: 2, reg: gp21, asm: "ADDL", commutative: true, resultInArg0: true}, // arg0 + arg1
|
||||
{name: "ADDW", argLength: 2, reg: gp21, asm: "ADDL", commutative: true, resultInArg0: true}, // arg0 + arg1
|
||||
{name: "ADDB", argLength: 2, reg: gp21, asm: "ADDL", commutative: true, resultInArg0: true}, // arg0 + arg1
|
||||
{name: "ADDQconst", argLength: 1, reg: gp11, asm: "ADDQ", aux: "Int64", resultInArg0: true, typ: "UInt64"}, // arg0 + auxint
|
||||
{name: "ADDLconst", argLength: 1, reg: gp11, asm: "ADDL", aux: "Int32", resultInArg0: true}, // arg0 + auxint
|
||||
{name: "ADDWconst", argLength: 1, reg: gp11, asm: "ADDL", aux: "Int16", resultInArg0: true}, // arg0 + auxint
|
||||
{name: "ADDBconst", argLength: 1, reg: gp11, asm: "ADDL", aux: "Int8", resultInArg0: true}, // arg0 + auxint
|
||||
{name: "ADDQ", argLength: 2, reg: gp21sp, asm: "ADDQ", commutative: true}, // arg0 + arg1
|
||||
{name: "ADDL", argLength: 2, reg: gp21sp, asm: "ADDL", commutative: true}, // arg0 + arg1
|
||||
{name: "ADDW", argLength: 2, reg: gp21sp, asm: "ADDL", commutative: true}, // arg0 + arg1
|
||||
{name: "ADDB", argLength: 2, reg: gp21sp, asm: "ADDL", commutative: true}, // arg0 + arg1
|
||||
{name: "ADDQconst", argLength: 1, reg: gp11sp, asm: "ADDQ", aux: "Int64", typ: "UInt64"}, // arg0 + auxint
|
||||
{name: "ADDLconst", argLength: 1, reg: gp11sp, asm: "ADDL", aux: "Int32"}, // arg0 + auxint
|
||||
{name: "ADDWconst", argLength: 1, reg: gp11sp, asm: "ADDL", aux: "Int16"}, // arg0 + auxint
|
||||
{name: "ADDBconst", argLength: 1, reg: gp11sp, asm: "ADDL", aux: "Int8"}, // arg0 + auxint
|
||||
|
||||
{name: "SUBQ", argLength: 2, reg: gp21, asm: "SUBQ", resultInArg0: true}, // arg0 - arg1
|
||||
{name: "SUBL", argLength: 2, reg: gp21, asm: "SUBL", resultInArg0: true}, // arg0 - arg1
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ type opData struct {
|
|||
rematerializeable bool
|
||||
argLength int32 // number of arguments, if -1, then this operation has a variable number of arguments
|
||||
commutative bool // this operation is commutative (e.g. addition)
|
||||
resultInArg0 bool // prefer v and v.Args[0] to be allocated to the same register
|
||||
resultInArg0 bool // v and v.Args[0] must be allocated to the same register
|
||||
}
|
||||
|
||||
type blockData struct {
|
||||
|
|
@ -155,6 +155,12 @@ func genOp() {
|
|||
}
|
||||
if v.resultInArg0 {
|
||||
fmt.Fprintln(w, "resultInArg0: true,")
|
||||
if v.reg.inputs[0] != v.reg.outputs[0] {
|
||||
log.Fatalf("input[0] and output registers must be equal for %s", v.name)
|
||||
}
|
||||
if v.commutative && v.reg.inputs[1] != v.reg.outputs[0] {
|
||||
log.Fatalf("input[1] and output registers must be equal for %s", v.name)
|
||||
}
|
||||
}
|
||||
if a.name == "generic" {
|
||||
fmt.Fprintln(w, "generic:true,")
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@ type opInfo struct {
|
|||
generic bool // this is a generic (arch-independent) opcode
|
||||
rematerializeable bool // this op is rematerializeable
|
||||
commutative bool // this operation is commutative (e.g. addition)
|
||||
resultInArg0 bool // prefer v and v.Args[0] to be allocated to the same register
|
||||
resultInArg0 bool // v and v.Args[0] must be allocated to the same register
|
||||
}
|
||||
|
||||
type inputInfo struct {
|
||||
|
|
|
|||
|
|
@ -971,15 +971,14 @@ var opcodeTable = [...]opInfo{
|
|||
},
|
||||
},
|
||||
{
|
||||
name: "ADDQ",
|
||||
argLen: 2,
|
||||
commutative: true,
|
||||
resultInArg0: true,
|
||||
asm: x86.AADDQ,
|
||||
name: "ADDQ",
|
||||
argLen: 2,
|
||||
commutative: true,
|
||||
asm: x86.AADDQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -988,15 +987,14 @@ var opcodeTable = [...]opInfo{
|
|||
},
|
||||
},
|
||||
{
|
||||
name: "ADDL",
|
||||
argLen: 2,
|
||||
commutative: true,
|
||||
resultInArg0: true,
|
||||
asm: x86.AADDL,
|
||||
name: "ADDL",
|
||||
argLen: 2,
|
||||
commutative: true,
|
||||
asm: x86.AADDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1005,15 +1003,14 @@ var opcodeTable = [...]opInfo{
|
|||
},
|
||||
},
|
||||
{
|
||||
name: "ADDW",
|
||||
argLen: 2,
|
||||
commutative: true,
|
||||
resultInArg0: true,
|
||||
asm: x86.AADDL,
|
||||
name: "ADDW",
|
||||
argLen: 2,
|
||||
commutative: true,
|
||||
asm: x86.AADDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1022,15 +1019,14 @@ var opcodeTable = [...]opInfo{
|
|||
},
|
||||
},
|
||||
{
|
||||
name: "ADDB",
|
||||
argLen: 2,
|
||||
commutative: true,
|
||||
resultInArg0: true,
|
||||
asm: x86.AADDL,
|
||||
name: "ADDB",
|
||||
argLen: 2,
|
||||
commutative: true,
|
||||
asm: x86.AADDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1039,11 +1035,10 @@ var opcodeTable = [...]opInfo{
|
|||
},
|
||||
},
|
||||
{
|
||||
name: "ADDQconst",
|
||||
auxType: auxInt64,
|
||||
argLen: 1,
|
||||
resultInArg0: true,
|
||||
asm: x86.AADDQ,
|
||||
name: "ADDQconst",
|
||||
auxType: auxInt64,
|
||||
argLen: 1,
|
||||
asm: x86.AADDQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
|
|
@ -1055,11 +1050,10 @@ var opcodeTable = [...]opInfo{
|
|||
},
|
||||
},
|
||||
{
|
||||
name: "ADDLconst",
|
||||
auxType: auxInt32,
|
||||
argLen: 1,
|
||||
resultInArg0: true,
|
||||
asm: x86.AADDL,
|
||||
name: "ADDLconst",
|
||||
auxType: auxInt32,
|
||||
argLen: 1,
|
||||
asm: x86.AADDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
|
|
@ -1071,11 +1065,10 @@ var opcodeTable = [...]opInfo{
|
|||
},
|
||||
},
|
||||
{
|
||||
name: "ADDWconst",
|
||||
auxType: auxInt16,
|
||||
argLen: 1,
|
||||
resultInArg0: true,
|
||||
asm: x86.AADDL,
|
||||
name: "ADDWconst",
|
||||
auxType: auxInt16,
|
||||
argLen: 1,
|
||||
asm: x86.AADDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
|
|
@ -1087,11 +1080,10 @@ var opcodeTable = [...]opInfo{
|
|||
},
|
||||
},
|
||||
{
|
||||
name: "ADDBconst",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
resultInArg0: true,
|
||||
asm: x86.AADDL,
|
||||
name: "ADDBconst",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AADDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
|
|
@ -1109,8 +1101,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASUBQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1125,8 +1117,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASUBL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1141,8 +1133,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASUBL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1157,8 +1149,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASUBL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1174,7 +1166,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASUBQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1190,7 +1182,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASUBL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1206,7 +1198,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASUBL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1222,7 +1214,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASUBL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1238,8 +1230,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AIMULQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1255,8 +1247,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AIMULL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1272,8 +1264,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AIMULW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1289,8 +1281,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AIMULW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1306,7 +1298,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AIMULQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1322,7 +1314,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AIMULL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1338,7 +1330,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AIMULW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1354,7 +1346,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AIMULW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1489,8 +1481,8 @@ var opcodeTable = [...]opInfo{
|
|||
resultInArg0: true,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1686,8 +1678,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AANDQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1703,8 +1695,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AANDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1720,8 +1712,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AANDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1737,8 +1729,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AANDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1754,7 +1746,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AANDQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1770,7 +1762,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AANDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1786,7 +1778,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AANDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1802,7 +1794,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AANDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1818,8 +1810,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AORQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1835,8 +1827,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1852,8 +1844,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1869,8 +1861,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1886,7 +1878,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AORQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1902,7 +1894,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1918,7 +1910,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1934,7 +1926,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1950,8 +1942,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AXORQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1967,8 +1959,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AXORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -1984,8 +1976,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AXORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2001,8 +1993,8 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AXORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2018,7 +2010,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AXORQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2034,7 +2026,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AXORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2050,7 +2042,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AXORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2066,7 +2058,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AXORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2334,11 +2326,11 @@ var opcodeTable = [...]opInfo{
|
|||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 2}, // CX
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
},
|
||||
},
|
||||
|
|
@ -2350,11 +2342,11 @@ var opcodeTable = [...]opInfo{
|
|||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 2}, // CX
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
},
|
||||
},
|
||||
|
|
@ -2366,11 +2358,11 @@ var opcodeTable = [...]opInfo{
|
|||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 2}, // CX
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
},
|
||||
},
|
||||
|
|
@ -2382,11 +2374,11 @@ var opcodeTable = [...]opInfo{
|
|||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 2}, // CX
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
},
|
||||
},
|
||||
|
|
@ -2398,7 +2390,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASHLQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2414,7 +2406,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASHLL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2430,7 +2422,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASHLL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2446,7 +2438,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASHLL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2462,11 +2454,11 @@ var opcodeTable = [...]opInfo{
|
|||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 2}, // CX
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
},
|
||||
},
|
||||
|
|
@ -2478,11 +2470,11 @@ var opcodeTable = [...]opInfo{
|
|||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 2}, // CX
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
},
|
||||
},
|
||||
|
|
@ -2494,11 +2486,11 @@ var opcodeTable = [...]opInfo{
|
|||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 2}, // CX
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
},
|
||||
},
|
||||
|
|
@ -2510,11 +2502,11 @@ var opcodeTable = [...]opInfo{
|
|||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 2}, // CX
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
},
|
||||
},
|
||||
|
|
@ -2526,7 +2518,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASHRQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2542,7 +2534,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASHRL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2558,7 +2550,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASHRW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2574,7 +2566,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASHRB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2590,11 +2582,11 @@ var opcodeTable = [...]opInfo{
|
|||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 2}, // CX
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
},
|
||||
},
|
||||
|
|
@ -2606,11 +2598,11 @@ var opcodeTable = [...]opInfo{
|
|||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 2}, // CX
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
},
|
||||
},
|
||||
|
|
@ -2622,11 +2614,11 @@ var opcodeTable = [...]opInfo{
|
|||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 2}, // CX
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
},
|
||||
},
|
||||
|
|
@ -2638,11 +2630,11 @@ var opcodeTable = [...]opInfo{
|
|||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 2}, // CX
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
},
|
||||
},
|
||||
|
|
@ -2654,7 +2646,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASARQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2670,7 +2662,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASARL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2686,7 +2678,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASARW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2702,7 +2694,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ASARB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2718,7 +2710,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AROLQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2734,7 +2726,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AROLL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2750,7 +2742,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AROLW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2766,7 +2758,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.AROLB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2781,7 +2773,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ANEGQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2796,7 +2788,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ANEGL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2811,7 +2803,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ANEGL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2826,7 +2818,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ANEGL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2841,7 +2833,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ANOTQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2856,7 +2848,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ANOTL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2871,7 +2863,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ANOTL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2886,7 +2878,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ANOTL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2900,7 +2892,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ABSFQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2914,7 +2906,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ABSFL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2928,7 +2920,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ABSFW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2942,7 +2934,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ABSRQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2956,7 +2948,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ABSRL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2970,7 +2962,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ABSRW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -2987,7 +2979,7 @@ var opcodeTable = [...]opInfo{
|
|||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 8589934592}, // FLAGS
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934593, // AX FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -3004,7 +2996,7 @@ var opcodeTable = [...]opInfo{
|
|||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 8589934592}, // FLAGS
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934593, // AX FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -3021,7 +3013,7 @@ var opcodeTable = [...]opInfo{
|
|||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 8589934592}, // FLAGS
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934593, // AX FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -3038,7 +3030,7 @@ var opcodeTable = [...]opInfo{
|
|||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 8589934592}, // FLAGS
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934593, // AX FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -3055,7 +3047,7 @@ var opcodeTable = [...]opInfo{
|
|||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 8589934592}, // FLAGS
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934593, // AX FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -3072,7 +3064,7 @@ var opcodeTable = [...]opInfo{
|
|||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 8589934592}, // FLAGS
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934593, // AX FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -3087,7 +3079,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ABSWAPQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
@ -3102,7 +3094,7 @@ var opcodeTable = [...]opInfo{
|
|||
asm: x86.ABSWAPL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||
},
|
||||
clobbers: 8589934592, // FLAGS
|
||||
outputs: []regMask{
|
||||
|
|
|
|||
|
|
@ -527,6 +527,18 @@ func (s *regAllocState) advanceUses(v *Value) {
|
|||
}
|
||||
}
|
||||
|
||||
// liveAfterCurrentInstruction reports whether v is live after
|
||||
// the current instruction is completed. v must be used by the
|
||||
// current instruction.
|
||||
func (s *regAllocState) liveAfterCurrentInstruction(v *Value) bool {
|
||||
u := s.values[v.ID].uses
|
||||
d := u.dist
|
||||
for u != nil && u.dist == d {
|
||||
u = u.next
|
||||
}
|
||||
return u != nil && u.dist > d
|
||||
}
|
||||
|
||||
// Sets the state of the registers to that encoded in regs.
|
||||
func (s *regAllocState) setState(regs []endReg) {
|
||||
s.freeRegs(s.used)
|
||||
|
|
@ -891,6 +903,27 @@ func (s *regAllocState) regalloc(f *Func) {
|
|||
args[i.idx] = s.allocValToReg(v.Args[i.idx], i.regs, true, v.Line)
|
||||
}
|
||||
|
||||
// If the output clobbers the input register, and the input register is
|
||||
// live beyond the instruction, make another copy of the input register so
|
||||
// we don't have to reload the value from the spill location.
|
||||
if opcodeTable[v.Op].resultInArg0 &&
|
||||
s.liveAfterCurrentInstruction(v.Args[0]) &&
|
||||
countRegs(s.values[v.Args[0].ID].regs) == 1 {
|
||||
|
||||
if opcodeTable[v.Op].commutative &&
|
||||
(!s.liveAfterCurrentInstruction(v.Args[1]) ||
|
||||
countRegs(s.values[v.Args[1].ID].regs) > 1) {
|
||||
// Input #1 is dead after the instruction, or we have
|
||||
// more than one copy of it in a register. Either way,
|
||||
// use that input as the one that is clobbered.
|
||||
args[0], args[1] = args[1], args[0]
|
||||
} else {
|
||||
m := s.compatRegs(v.Args[0].Type)
|
||||
m &^= s.values[v.Args[0].ID].regs // a register not already holding v.Args[0]
|
||||
s.allocValToReg(v.Args[0], m, true, v.Line)
|
||||
}
|
||||
}
|
||||
|
||||
// Now that all args are in regs, we're ready to issue the value itself.
|
||||
// Before we pick a register for the output value, allow input registers
|
||||
// to be deallocated. We do this here so that the output can use the
|
||||
|
|
@ -908,19 +941,9 @@ func (s *regAllocState) regalloc(f *Func) {
|
|||
s.f.Fatalf("bad mask %s\n", v.LongString())
|
||||
}
|
||||
if opcodeTable[v.Op].resultInArg0 {
|
||||
// Output must use the same register as input 0.
|
||||
r := register(s.f.getHome(args[0].ID).(*Register).Num)
|
||||
if (mask&^s.used)>>r&1 != 0 {
|
||||
mask = regMask(1) << r
|
||||
}
|
||||
if opcodeTable[v.Op].commutative {
|
||||
r := register(s.f.getHome(args[1].ID).(*Register).Num)
|
||||
if (mask&^s.used)>>r&1 != 0 {
|
||||
mask = regMask(1) << r
|
||||
}
|
||||
}
|
||||
// TODO: enforce resultInArg0 always, instead of treating it
|
||||
// as a hint. Then we don't need the special cases adding
|
||||
// moves all throughout ssa.go:genValue.
|
||||
mask = regMask(1) << r
|
||||
}
|
||||
r := s.allocReg(v, mask)
|
||||
s.assignReg(r, v, v)
|
||||
|
|
|
|||
|
|
@ -16653,6 +16653,17 @@ func rewriteValueAMD64_OpAMD64SUBBconst(v *Value, config *Config) bool {
|
|||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (SUBBconst [c] x)
|
||||
// cond:
|
||||
// result: (ADDBconst [int64(int8(-c))] x)
|
||||
for {
|
||||
c := v.AuxInt
|
||||
x := v.Args[0]
|
||||
v.reset(OpAMD64ADDBconst)
|
||||
v.AuxInt = int64(int8(-c))
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (SUBBconst (MOVBconst [d]) [c])
|
||||
// cond:
|
||||
// result: (MOVBconst [int64(int8(d-c))])
|
||||
|
|
@ -16751,6 +16762,17 @@ func rewriteValueAMD64_OpAMD64SUBLconst(v *Value, config *Config) bool {
|
|||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (SUBLconst [c] x)
|
||||
// cond:
|
||||
// result: (ADDLconst [int64(int32(-c))] x)
|
||||
for {
|
||||
c := v.AuxInt
|
||||
x := v.Args[0]
|
||||
v.reset(OpAMD64ADDLconst)
|
||||
v.AuxInt = int64(int32(-c))
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (SUBLconst (MOVLconst [d]) [c])
|
||||
// cond:
|
||||
// result: (MOVLconst [int64(int32(d-c))])
|
||||
|
|
@ -16854,6 +16876,20 @@ func rewriteValueAMD64_OpAMD64SUBQconst(v *Value, config *Config) bool {
|
|||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (SUBQconst [c] x)
|
||||
// cond: c != -(1<<31)
|
||||
// result: (ADDQconst [-c] x)
|
||||
for {
|
||||
c := v.AuxInt
|
||||
x := v.Args[0]
|
||||
if !(c != -(1 << 31)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpAMD64ADDQconst)
|
||||
v.AuxInt = -c
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (SUBQconst (MOVQconst [d]) [c])
|
||||
// cond:
|
||||
// result: (MOVQconst [d-c])
|
||||
|
|
@ -16955,6 +16991,17 @@ func rewriteValueAMD64_OpAMD64SUBWconst(v *Value, config *Config) bool {
|
|||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (SUBWconst [c] x)
|
||||
// cond:
|
||||
// result: (ADDWconst [int64(int16(-c))] x)
|
||||
for {
|
||||
c := v.AuxInt
|
||||
x := v.Args[0]
|
||||
v.reset(OpAMD64ADDWconst)
|
||||
v.AuxInt = int64(int16(-c))
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (SUBWconst (MOVWconst [d]) [c])
|
||||
// cond:
|
||||
// result: (MOVWconst [int64(int16(d-c))])
|
||||
|
|
|
|||
Loading…
Reference in New Issue