J. Neuschäfer 139a0931a3 Fix memory barriers on ARMv5 ... The ARM926EJ-S Technical Reference Manual states: > You can only access CP15 registers with MRC and MCR instructions in a > privileged mode. CDP, LDC, STC, MCRR, and MRRC instructions, and unprivileged > MRC or MCR instructions to CP15 cause the Undefined instruction exception to > be taken. Furthermore, `MCR p15, 0, <Rd>, c7, c10, 5` (later called Data Memory Barrier) is not specified for the ARM926. Thus, SDL should not use these cache instructions on ARMv5.		2024-01-05 09:00:47 -08:00
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SDL3	Fix memory barriers on ARMv5	2024-01-05 09:00:47 -08:00
build_config	Updated copyright for 2024	2024-01-01 13:15:26 -08:00